Referenceless clock recovery circuit with wide frequency acquisition range

Patent metadata

Field	Value
Publication number	US-9525544-B2
Application number	US-201514716593-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	May 19, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A full-rate referenceless clock-data recovery architecture with neither a frequency detector nor a lock detector that allows both frequency and phase locking in a single loop. According to one embodiment, a referenceless clock data recovery (CDR) circuit, comprises a digital control circuit (DCC), a phase and strobe point detector circuit (PSPD), and an LC voltage control oscillator (LC VCO) electrically coupled to the PSPD and DCC such that a frequency of the LC VCO decreases when a negative strobe point is detected and an initial frequency of the LC VCO is higher than an input data bit rate.

First claim

What is claimed is:

1. A referenceless clock data recovery (CDR) circuit, comprising:
a digital control circuit (DCC) configured to generate a strobe point voltage (Vsp);
a phase and strobe point detector circuit (PSPD) electrically coupled to the DCC and configured to detect the strobe point voltage (Vsp) generated by the DCC and set a strobe point (SP) according to the strobe point voltage (V sp ); and
an LC voltage control oscillator (LC VCO) electrically coupled to the PSP…

Assignees

• Univ California

Inventors

• Green Michael M
• Huang Sui

Classifications

• H04L7/0004

  Electricity · mapped topic

• H03J2200/10

  Electricity · mapped topic

• H04L7/033 Primary

  Electricity · mapped topic

• H04L7/0087

  Electricity · mapped topic

• H03L7/0891

  Electricity · mapped topic