Semiconductor device and method of formation

Patent metadata

Field	Value
Publication number	US-9525072-B2
Application number	US-201414455992-A
Country	US
Kind code	B2
Filing date	Aug 11, 2014
Priority date	Aug 11, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first active area over the substrate;
a second active area over the substrate;
a graphene channel between the first active area and the second active area, the graphene channel having a first side and a second side;
a dielectric layer between the substrate and the graphene channel;
an in-plane gate extending around the first active area from the first side of the graphene channel to the second side of the graphene channel; and
a bottom gate in contact with a bottom surface of the substrate.

2. The semiconductor device of claim 1 , the in-plane gate comprising graphene.

3. The semiconductor device of claim 1 , at least one of the first active area or the second active area comprising graphene.

4. The semiconductor device of claim 1 , at least one of the first active area, the second active area, or the in-plane gate comprising at least one of gold, copper or nickel.

5. The semiconductor device of claim 1 , wherein:
the in-plane gate comprises at least one of gold, copper or nickel; and
the at least one of gold, copper or nickel of the in-plane gate is in-plane with the graphene channel.

6. The semiconductor device of claim 1 , wherein the graphene channel has a channel length of about 5 micrometers to about 75 micrometers.

7. The semiconductor device of claim 1 , wherein the graphene channel has a channel width of about 1 micrometer to about 25 micrometers.

8. The semiconductor device of claim 1 , wherein the graphene channel has a channel height of about 1 angstrom to about 500 angstroms.

9. The semiconductor device of claim 1 , wherein the bottom surface of the substrate lies in a first plane and the first active area, the second active area, the graphene channel, and the in-plane gate intersect a second plane parallel to the first plane.

10. The semiconductor device of claim 1 , the substrate comprising silicon and the dielectric layer comprising silicon oxide.

11. A semiconductor device, comprising:
a substrate;
a dielectric layer over the substrate;
a first active area over the dielectric layer;
a second active area over the dielectric layer;
a graphene channel over the dielectric layer and between the first active area and the second active area, the graphene channel having a first side and a second side; and
a first in-plane gate over the dielectric layer and proximate the first side; and
a bottom gate in contact with a bottom surface of the substrate.

12. The semiconductor device of claim 11 , comprising:
a second in-plane gate proximate the second side, the second in-plane gate comprising graphene.

13. The semiconductor device of claim 11 , the first in-plane gate comprising graphene.

14. The semiconductor device of claim 11 , wherein the graphene channel has a channel length of about 5 micrometers to about 75 micrometers.

15. The semiconductor device of claim 11 , wherein the graphene channel has a channel width of about 1 micrometer to about 25 micrometers.

16. The semiconductor device of claim 11 , wherein the graphene channel has a channel height of about 1 angstrom to about 500 angstroms.

17. The semiconductor device of claim 11 , at least one of the first active area or the second active area comprising graphene.

18. A semiconductor device, comprising:
a substrate;
a first active area over the substrate;
a second active area over the substrate;
a graphene channel between the first active area and the second active area, the graphene channel having a first side and a second side;
a dielectric layer between the substrate and the graphene channel;
an in-plane gate extending around the first active area and proximate the first side of the graphene channel; and
a bottom gate in contact with a bottom surface of the substrate.

19. The semiconductor device of claim 18 , wherein the in-plane gate extends from the first side of the graphene channel to the second side of the graphene channel.

20. The semiconductor device of claim 18 , wherein the in-plane gate extends around at least three sides of the first active area.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Lin Meng-Yu
• Lin Shih-Yen
• Lee Si-Chen

Classifications

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D62/882 Primary

  Graphene · CPC title

• C01B32/20

  Graphite · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title