Semiconductor device with combined passive device on chip back side

Patent metadata

Field	Value
Publication number	US-9524932-B2
Application number	US-201514791051-A
Country	US
Kind code	B2
Filing date	Jul 2, 2015
Priority date	Jul 31, 2013
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor chip, the method comprising:
forming a semiconductor device on a first side of a substrate;
forming an electrically insulating layer on at least a portion of a second side of the substrate, wherein the second side is opposite the first side;
forming a passive device on at least a portion of the electrically insulating layer, wherein the passive device is electrically insulated from the semiconductor device;
forming a chip carrier including at least a first portion and a second portion, wherein the first portion is electrically isolated from the second portion, and wherein the chip carrier comprises an electrically conductive material; and
attaching the first portion of the chip carrier to the passive device.

2. The method of claim 1 , wherein the portion of the second side of the substrate is a first portion of the second side of the substrate, wherein forming the passive device further comprises forming a metal layer on at least a portion of the electrically insulating layer and on at least a second portion of the second side of the substrate, the method further comprising:
forming a layer stack over at least a second portion of the metal layer, wherein the second portion of the metal layer is on the second portion of the second side of the substrate.

3. The method of claim 1 , wherein attaching the first portion of the chip carrier to the passive device comprises mechanically coupling at least a section of the first portion of the chip carrier directly to the passive device, the method further comprising:
forming a first electrode between a first plate of the passive device and the first portion of the chip carrier, wherein the first electrode is electrically coupled to the first plate of the passive device, and wherein the first electrode is mechanically affixed to the first portion of the chip carrier; and
forming a second electrode between a second plate of the passive device and the second portion of the chip carrier, wherein the second electrode is electrically coupled to the second plate of the passive device, and wherein the second electrode is mechanically coupled to the second portion of the chip carrier.

4. The method of claim 1 , wherein forming the electrically insulating layer comprises forming an oxide layer, wherein forming the passive device comprises forming a capacitor device, and wherein forming the capacitor device comprises:
forming a first metal layer on at least a portion of the oxide layer;
forming a dielectric layer on at least a portion of the first metal layer;
forming a second metal layer on at least a portion of the dielectric layer; and
forming an isolation to chip carrier layer on at least a portion of the second metal layer.

5. The method of claim 4 , wherein forming the semiconductor device comprises forming a field effect transistor configured to have current flow approximately between the first side and the second side of the substrate, and wherein the portion of the second side of the substrate is a first portion of the second side of the substrate.

6. The method of claim 5 , wherein the portion of the first metal layer is a first portion of the first metal layer, wherein the portion of the second metal layer is a first portion of the second metal layer, the method further comprising:
forming a layer stack over at least a portion of a second portion of the second side of the substrate;
forming a first electrode on at least a second portion of the first metal layer;
forming a second electrode on a second portion of the second metal layer;
mechanically coupling the first portion of a chip carrier to at least a portion of the layer stack;
mechanically coupling the second portion of the chip carrier to the first electrode; and
mechanically coupling a third portion of the chip carrier to at least a portion of the isolation to chip carrier layer and the second electrode, wherein the first, second, and third portions of the chip carrier are electrically isolated from each other.

7. The method of claim 5 , wherein the portion of the second side of the substrate is a first portion of the second side of the substrate, wherein forming the first metal layer comprises forming the first metal layer on at least a second portion of the second side of the substrate, the method further comprising:
forming a layer stack over at least a second portion of the first metal layer, wherein forming the second portion of the first metal layer comprises forming the second portion of the first metal layer on the second portion of the second side of the substrate.

8. The method of claim 1 , wherein forming the semiconductor device comprises forming at least one of:
a light emitting diode (LED);
a field effect transistor (FET); or
a vertical FET.

9. The method of claim 1 , wherein forming the passive device comprises forming a trench structure.

10. The method of claim 1 , wherein the portion of the electrically insulating layer is a first portion of the electrically insulating layer, and wherein the passive device is a first passive device, the method further comprising:
forming a second passive device on at least a second portion of the electrically insulating layer on the second side of the substrate, wherein the second passive device is electrically insulated from the semiconductor device and the first passive device.

11. A method of manufacturing a semiconductor chip package, the method comprising:
forming a semiconductor device on a first side of a substrate;
forming an electrically insulating layer on at least a portion of a second side of the substrate;
forming a capacitor device on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device;
forming a chip carrier including at least a first portion and a second portion, wherein the first portion is electrically isolated from the second portion, and wherein the chip carrier comprises an electrically conductive material; and
attaching the first portion of the chip carrier to the capacitor device.

12. The method of claim 11 , wherein attaching the first portion of the chip carrier to the capacitor device comprises: mechanically coupling at least a section of the first portion of the chip carrier directly to the capacitor device, the method further comprising:
forming a first electrode between a first plate of the capacitor device and the first portion of the chip carrier, wherein the first electrode is electrically coupled to the first plate of the capacitor device, and wherein the first electrode is mechanically affixed to the first portion of the chip carrier;
forming a second electrode between a second plate of the capacitor device and the first portion of the chip carrier, wherein the second electrode is electrically coupled to the second plate of the capacitor device; and
mechanically coupling the second electrode to the second portion of the chip carrier.

13. The method of claim 11 , wherein forming the semiconductor device comprises forming a field effect transistor configured to have current flow approximately between the first side and the second side of the substrate, wherein the portion of the second side of the substrate is a first portion of the second side of the substrate, wherein forming the electrically insulating layer comprises forming an oxide layer, and wherein forming the capacitor device comprises:
forming a first metal layer on at least a portion of the oxide layer;
forming a dielectric layer on at least a portion of the first metal layer;
forming

Assignees

• Infineon Technologies Austria Ag

Inventors

• Munding Andreas
• Gruber Martin

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/071

  Connecting or disconnecting · CPC title

• H10W70/421

  Shapes or dispositions · CPC title