Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same

Patent metadata

Field	Value
Publication number	US-9524922-B2
Application number	US-201514665428-A
Country	US
Kind code	B2
Filing date	Mar 23, 2015
Priority date	Jun 19, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction.

First claim

What is claimed is:

1. An integrated circuit comprising:
first and second vias, each of the first and second vias being configured to penetrate a plurality of chips and configured to provide a signal transmission route between the plurality of chips;
a first buffer connected between an output terminal of the first via and a detour node, and configured to receive a signal transmitted from the first via;
a second buffer connected between an output terminal of the second via and the detour node, and configured to receive a signal transmitted from the second via;
a first detour circuit configured to receive a signal transmitted through the second buffer;
a second detour circuit configured to receive a signal transmitted through the first buffer, an output of the first buffer, an output of the second buffer, an input of the first detour circuit, and an input of the second detour circuit being connected with the detour node together;
a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, based on a state of signal transmission through the first via; and
a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit, based on a state of signal transmission through the second via,
wherein each of the first and second buffers and the first and second detour circuits is configured to transmit a signal in only one direction.

2. The integrated circuit of claim 1 , wherein when the signal transmission through the first via is disabled, the signal transmitted from the second via is provided to the first selector through the second buffer and the first detour circuit.

3. The integrated circuit of claim 2 , wherein the first selector is configured to output the signal transmitted through the first detour circuit.

4. The integrated circuit of claim 1 , further comprising:
a first controller configured to control operations of the first buffer, the first detour circuit, and the first selector; and
a second controller configured to control operations of the second buffer, the second detour circuit, and the second selector.

5. The integrated circuit of claim 4 , wherein the first controller is configured to determine whether the signal transmission through the first via is normal or disabled, and
the second controller is configured to determine whether the signal transmission through the second via is normal or disabled.

6. The integrated circuit of claim 4 , wherein when the signal transmission through the second via is disabled:
the first buffer is configured to be turned on according to a control of the first controller, and configured to transmit the signal transmitted from the first via to the second detour circuit, and
the second detour circuit is configured to be turned on according to a control of the second controller, and configured to transmit the signal transmitted through the first buffer to the second selector.

7. The integrated circuit of claim 6 , wherein the second selector is configured to output the signal transmitted through the second detour circuit according to the control of the second controller.

8. The integrated circuit of claim 1 , further comprising a test circuit configured to receive a test signal at a test mode, and configured to transmit the received test signal to the detour node.

9. The integrated circuit of claim 8 , wherein the test circuit comprises:
a pass circuit configured to receive the test signal and configured to transmit the received test signal to the detour node; and
a test controller configured to control the pass circuit.

10. The integrated circuit of claim 8 , wherein at the test mode, the test signal transmitted to the detour node is transmitted to each of the first and second detour circuits.

11. The integrated circuit of claim 10 , wherein at the test mode, the first selector is configured to output the test signal transmitted through the first detour circuit, and the second selector is configured to output the test signal transmitted through the second detour circuit.

12. The integrated circuit of claim 1 , wherein at least one of the first and second buffers and the first and second detour circuits comprises a compensator configured to compensate a distortion of a transmitted signal.

13. The integrated circuit of claim 1 , further comprising:
a first delay circuit configured to delay the signal transmitted from the first via, configured to generate a first delayed signal, and configured to transmit the first delayed signal to the first selector; and
a second delay circuit configured to delay the signal transmitted from the second via, configured to generate a second delayed signal, and configured to transmit the second delayed signal to the second selector.

14. An integrated circuit package comprising:
a plurality of chips;
a plurality of vias configured to penetrate at least one of the plurality of chips, each of the plurality of vias being configured to provide a signal transmission route between the plurality of chips, the plurality of vias including a first via and a second via; and
a detour circuit configured to provide a detour route for the first via and the second via,
wherein the detour circuit includes,
a first buffer connected between an output terminal of the first via and a detour node, and configured to receive a signal transmitted from the first via;
a second buffer connected between an output terminal of the second via and the detour node, and configured to receive a signal transmitted from the second via;
a first detour circuit configured to receive a signal transmitted through the second buffer;
a second detour circuit configured to receive a signal transmitted through the first buffer, an output of the first buffer, an output of the second buffer, an input of the first detour circuit, and an input of the second detour circuit being connected with the detour node together;
a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, based on a state of signal transmission through the first via; and
a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit, based on a state of signal transmission through the second via, and
wherein each of the first and second buffers and the first and second detour circuits is configured to transmit a signal in only one direction.

15. The integrated circuit package of claim 14 , wherein when the signal transmission through the first via is disabled, the signal transmitted from the second via is provided to the first selector through the second buffer and the first detour circuit, and the first selector is configured to output the signal transmitted through the first detour circuit.

16. An integrated circuit comprising:
a first switch circuit connected between an output terminal of a first through-silicon via (TSV) and a detour node, and configured to receive a first signal transmitted from the first TSV;
a second switch circuit connected between an output terminal of a second TSV and the detour node, and configured to receive a second signal transmitted from the second TSV;
a third switch circuit configured to receive the second signal transmitted through the second switch circuit and the detour node;
a fourth switch circuit configured to receive the first signal transmitted throug

Assignees

• Samsung Electronics Co Ltd
• Snu R&Db Foundation

Inventors

• Lim Kyounghwan
• Park Hyoun Soo
• Kim Kee Sup
• Lee Bonghyun
• Rim Chul
• Choi Jungyun
• Kim Taewhan
• Park Heechun

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title