Annotations to identify objects in design generated by high level synthesis (HLS)

Patent metadata

Field	Value
Publication number	US-9524366-B1
Application number	US-201514731300-A
Country	US
Kind code	B1
Filing date	Jun 4, 2015
Priority date	Jun 4, 2015
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Methods and systems provide creating and reporting of path annotations and renaming a state node using the path annotations for high level synthesis (HLS). In an embodiment, a method to annotate a state node includes identifying labels and pragmas specified in a high-level language input model for wait statements and function calls, and can also accommodate loops. In an embodiment, a method to display and/or report annotation information for a given state node includes displaying a state node name, an associated path annotation, and/or an associated hierarchical path. In an embodiment, a method to rename a state node based on a user-specified name includes using annotation information to locate a target state node and associating the target state node with the user-specified name or an automatically-created name based on the user-specified name. In an embodiment, a name specified for a state node can persist through successive runs of an HLS tool.

First claim

What is claimed is:

1. A processor-implemented method for an electronic design and verification tool to synthesize a behavioral description of a circuit into a structural description of the circuit, the method comprising:
using a processor:
facilitating generation of the structural description of the circuit by:
parsing the behavioral description of the circuit to identify a first text and/or a second text;
defining a path annotation based on the identified first text and/or the identified second text; and
annotating a state node with the path annotation; and

generating the structural description of the circuit based on the facilitating.

2. The method of claim 1 , wherein the defining the path annotation includes, for each function call:
responsive to an identification of a first text, modifying the path annotation to include the first text; and
responsive to an identification of a wait statement, modifying the path annotation to include a second text associated with the wait statement.

3. The method of claim 1 , wherein the defining the path annotation includes, for each function call:
responsive to a determination, by the processor, that a first text is specified, modifying the path annotation to include the first text; and
responsive to a determination that a second text is associated with a wait statement, modifying the path annotation to include the second text associated with the wait statement.

4. The method of claim 3 , wherein the defining the path annotation further includes, for each function call:
responsive to a determination that the behavioral description of the circuit includes a function call missing one of a first text and a second text, modifying the path annotation to include an empty string;
responsive to a determination that the behavioral description of the circuit includes a function call with an unlabeled wait statement, modifying the path annotation to include an empty string; and
subsequent to processing all of the function calls, removing empty strings from the path annotation.

5. The method of claim 1 , wherein the facilitating further includes:
determining a call point of a function in the behavioral description of the circuit; and
wherein the defining the path annotation includes, for each function call:
responsive to a determination that the call point of the function is within an unrolled loop, modifying the path annotation to include an identification of an iteration of the unrolled loop;
responsive to an identification of a first text, modifying the path annotation to include the first text; and
responsive to an identification of a wait statement, modifying the path annotation to include a second text associated with the wait statement.

6. The method of claim 1 , further comprising:
generating, by the processor, a report including, for each behavior and each state node: an associated state name, the associated path annotation, and an associated hierarchical path.

7. The method of claim 1 , wherein the facilitating further includes:
receiving a name and the path annotation for the state node;
responsive to a determination that more than one state node match the received path annotation, creating a unique name for each of the matching state nodes based on the received path annotation and associating each of the created unique names with a respective one of the matching state nodes; and
responsive to a determination that a unique state node matches the received name, associating the unique state node with the received name;
wherein each of the created unique names associated with the respective one of the matching state nodes persists through at least two runs of the electronic design and verification tool.

8. The method of claim 7 , wherein the facilitating further includes:
responsive to the determination that more than one state node match the received path annotation, issuing an alert including each of the created unique names and the respective one of the matching state nodes.

9. The method of claim 1 , wherein the first text includes a pragma and the second text includes a label.

10. The method of claim 1 , wherein the path annotation is based on a string and the defining the path annotation includes modifying the string.

11. An electronic design and verification system for synthesizing a behavioral description of a circuit to generate a structural description of the circuit, the system comprising:
a storage apparatus to store a state node and the behavioral description of the circuit; and
a processor including:
a path annotation component configured to:
parse the behavioral description of the circuit to identify a first text and/or a second text;
define a path annotation based on the identified first text and/or the identified second text; and
annotate the state node with the path annotation; and

an output generator component configured to generate the structural description of the circuit based on the path annotation.

12. The system of claim 11 , wherein the path annotation component is further configured to, for each function call of the behavioral description of the circuit:
responsive to an identification of a first text, modify the path annotation to include the first text; and
responsive to an identification of a wait statement, modify the path annotation to include a second text associated with the wait statement.

13. The system of claim 12 , wherein the path annotation component is further configured to, for each function call of the behavioral description of the circuit:
responsive to a determination that a first text is unspecified, modify the path annotation to include an empty string;
responsive to a determination that a wait statement is unlabeled, modify the path annotation to include an empty string; and
subsequent to processing all of the function calls, remove empty strings from the path annotation.

14. The system of claim 11 , wherein the path annotation component is further configured to:
determine a call point of a function in source code; and
wherein the defining the path annotation includes, for each function call:
responsive to a determination that the call point of the function is within an unrolled loop, modifying the path annotation to include an identification of an iteration of the unrolled loop;
responsive to an identification of a first text, modifying the path annotation to include the first text; and
responsive to an identification of a wait statement, modifying the path annotation to include a second text associated with the wait statement.

15. The system of claim 11 , wherein the processor further includes a naming component, the naming component configured to:
receive a name and a path annotation for the state node;
responsive to a determination that more than one state node match the received path annotation, create a unique name for each of the matching state nodes based on the received name and associating each of the created unique names with a respective one of the matching state nodes; and
responsive to a determination that a unique state node matches the received path annotation, associate the unique state node with the received name;
wherein each of the created unique names associated with the respective one of the matching state nodes persists through at least two runs of the electronic design and verification tool.

16. The system of claim 15 , wherein in an initial mode of operation:
the processor receives: the behavioral description of the circuit, the name for the state node, and a synthesizing script including instructions for the pa

Assignees

• Cadence Design Systems Inc

Inventors

• Watanabe Yosinori
• Balarin Felice
• Tallapally Abhinav
• Ghijsen Walter Johan
• Meyer Michael J
• Solden Sherry
• Van Campenhout David
• Simion Viorica

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F17/241

  Physics · mapped topic

• G06F17/2705

  Physics · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic