Synthesis of clock gated circuit

Patent metadata

Field	Value
Publication number	US-9003339-B2
Application number	US-201414200839-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 7, 2013
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements.

First claim

We claim:

1. A non-transitory computer-readable storage medium having instructions stored therein for causing a processor to perform a process of synthesizing a behavioral description of a circuit into a structural description of the circuit, the process comprising:
receiving the behavioral description of the circuit, the behavioral description including a first statement that is associated with a condition;
identifying the condition associated with the first statement;
identifying one or more other statements associated with the first statement, including:
determining a downstream statement that depends on the first statement, and/or
determining an upstream statement upon which the first statement depends;

inferring one or more potential clock domains gated by the condition for logic associated with the first statement and the one or more other statements;
scheduling the logic associated with the first statement and the one or more other statements according to the one or more potential clock domains; and
generating the structural description of the circuit, the structural description including a structural description of the scheduled logic.

2. The non-transitory computer-readable storage medium of claim 1 , wherein the scheduling comprises:
selecting a subset of the one or more inferred potential clock domains based on at least one criteria; and
scheduling the logic associated with the first statement and the one or more other statements to the selected subset.

3. The non-transitory computer-readable storage medium of claim 1 , wherein the process further comprises:
determining that the condition is invariant across the one or more potential clock domains;
in response to the determining that the condition is invariant, defining a common gated clock domain that encompasses the one or more potential clock domains, wherein the common gated clock domain is to be clocked by a clock signal gated by the condition; and
scheduling the logic associated with the first statement and the one or more other statements to the defined common gated clock domain.

4. The non-transitory computer-readable storage medium of claim 3 , wherein the scheduling comprises:
scheduling the logic associated with the first statement and the one or more other statements into a plurality of pipeline stages of the defined common gated clock domain.

5. The non-transitory computer-readable storage medium of claim 1 , wherein:
the one or more potential clock domains include:
a first clock domain clocked by a first gated clock, the first gated clock being gated by a derivative of the condition; and
a second clock domain clocked by a second gated clock, the second gated clock being gated by the condition or another derivative of the condition; and

the scheduling comprises:
scheduling logic associated with the first statement to the first clock domain; and
scheduling logic associated with the one or more other statements to the second clock domain.

6. The non-transitory computer-readable storage medium of claim 1 , wherein the scheduling comprises:
assigning, based on a user directive, logic associated with the first statement and at least some of the one or more other statements to a particular gated clock domain, the particular gated clock domain being gated by the condition.

7. The non-transitory computer-readable storage medium of claim 1 , wherein the process further comprises:
translating the behavioral description of the circuit into an intermediate representation of the circuit, the intermediate representation including:
a data flow graph associated with the first statement; and
a plurality of other data flow graphs; and

analyzing the intermediate representation of the circuit, wherein the identifying the one or more other statements associated with the first statement is based on the analyzing the intermediate representation of the circuit.

8. The non-transitory computer-readable storage medium of claim 1 , wherein the condition is a logical combination of two or more conditions, and wherein an operation associated with the first statement is to be performed based on a satisfaction of the two or more conditions.

9. The non-transitory computer-readable storage medium of claim 1 , wherein the scheduling comprises:
iteratively:
evaluating the scheduled logic against at least a timing constraint and/or a power constraint; and
scheduling the logic associated with the first statement and the one or more other statements to a subset of the one or more inferred potential clock domains based on the evaluating.

10. The non-transitory computer-readable storage medium of claim 1 , wherein the scheduling comprises:
scheduling the logic to a first subset of the one or more inferred potential clock domains clocked based on the condition;
determining a power dissipation associated with the scheduled logic; and
rescheduling the logic according to a second subset of the one or more potential clock domains in response to the determining a power dissipation.

11. A computing device for synthesizing a first description of a circuit into a second description of the circuit, comprising:
a memory and a processor that are respectively adapted to store and execute instructions, including instructions organized into:
a front-end component that:
receives the first description of the circuit, the first description including a first statement that is associated with a condition;
identifies the condition associated with the first statement; and
determines a downstream statement that depends on the first statement and/or determines an upstream statement from which the first statement depends;

a scheduler component that:
infers one or more potential clock domains for logic associated with the first statement and for logic associated with the downstream statement and/or the upstream statement;
determines that the condition is invariant across the one or more inferred potential clock domains; and
schedules the logic associated with the first statement and one or more other statements with a particular clock domain gated by an invariant condition; and

an output generator component that:
generates the second description of the circuit, the second description including a description of the scheduled logic.

12. The computing device of claim 11 , wherein the first description of the circuit is a behavioral description of the circuit and the second description of the circuit is a structural description of the circuit.

13. The computing device of claim 11 , wherein the scheduler component also:
evaluates the scheduled logic against at least a timing constraint and/or a power constraint to obtain an evaluation result; and
based on the evaluation result, disassociates at least a portion of logic associated with the first statement and/or the upstream statement and/or the downstream statement from the particular clock domain.

14. The computing device of claim 11 , wherein the scheduler component also:
schedules logic associated with the first statement and the upstream statement and/or the downstream statement into pipeline stages associated with the particular clock domain.

15. The computing device of claim 11 , wherein the instructions are further organized into:
an input interface to
receive a user directive that includes:
a user defined clock domain gated by the condition; and
an assignment of the first statement and at least another statement in the first description of the circuit to the user defined clock domain.

16. A processor-implemented method for synthesizing a behaviora

Assignees

• Cadence Design Systems Inc

Inventors

• Jensen Mark
• Goodrich Andrew
• Fouron Valery

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2217/84

  Physics · mapped topic

• G06F17/505 Primary

  Physics · mapped topic