Instruction and logic for memory disambiguation in an out-of-order processor

Patent metadata

Field	Value
Publication number	US-9524170-B2
Application number	US-201314139171-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 23, 2013
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A system includes a processor with a front end to receive an instruction stream reordered by a software scheduler and including a plurality of memory operations and alias information indicating how a given memory operation may be evaluated. Furthermore, the processor includes a hardware scheduler to reorder, in hardware, the instruction stream for out-of-order execution. In addition, the processor includes a calculation module to determine, for a given memory operation and based upon the alias information, a checking range of memory atoms subsequent to the given memory operation and a virtual order of the memory operation. The virtual order indicates an original ordering of the instructions. The processor also includes an alias unit to reorder the instruction stream, determine whether the hardware reordering caused an error, and determine whether the software reordering caused an error based upon the checking range and the virtual order.

First claim

What is claimed is:

1. A processor, comprising:
a front end including circuitry to receive an instruction stream of memory operations as reordered by a software scheduler, each of the plurality of memory operations associated with a set of alias information;
a hardware scheduler including circuitry to reorder, in hardware, the instruction stream for out-of-order execution by resources of the processor;
a calculation module including circuitry to determine, for a given memory operation and based upon the set of alias information, a check range of memory atoms subsequent to the given memory operation in the instruction stream and a virtual order of the memory operation, the virtual order to indicate an original order of instructions; and
an alias unit including circuitry to:
after execution and before retirement of instructions of the instruction stream, reorder the instruction stream based on an order as received by the front end;
determine whether the reorder of the instruction stream in hardware and subsequent execution caused a data dependency error; and
determine, based upon the check range and the virtual order, whether the reorder of the instruction stream by the software scheduler and subsequent execution caused a data dependency error for the given memory operation when compared to the memory atoms.

2. The processor of claim 1 , wherein:
the alias information includes a high offset; and
the alias unit further includes circuitry to evaluate memory atoms ordered past the given memory operation plus the high offset, wherein the memory atoms would have executed before the given memory operation.

3. The processor of claim 2 , wherein the virtual order to indicate an original order of the instructions before reorder by the software scheduler is based upon a memory identification of the given memory operation and the high offset.

4. The processor of claim 1 , wherein:
the alias information includes a low offset; and
the alias unit further includes circuitry to evaluate memory atoms ordered between the given memory operation and the given memory operation plus the low offset, wherein the memory atoms would have executed after the given memory operation.

5. The processor of claim 1 , wherein the alias unit further includes circuitry to:
evaluate the given memory operation against the range of memory atoms with respect to a first set of criteria;
disregard elements of the range of memory atoms that indicate that comparison of a given memory atom with the given memory operation cannot produce a data dependency error; and
selectively evaluate the given memory operation against other elements of the range of memory atoms with respect to a second set of criteria.

6. The processor of claim 1 , wherein:
the alias information includes a high offset and a low offset; and
the alias unit further includes circuitry to:
evaluate memory atoms ordered past the given memory operation plus the high offset, wherein the memory atoms would have executed before the given memory operation;
evaluate memory atoms that ordered between the given memory operation and the given memory operation plus the low offset, wherein the memory atoms would have executed after the given memory operation; and
evaluate memory atoms ordered between the low offset and the high offset regardless of execution order.

7. The processor of claim 1 , wherein the alias unit further includes circuitry to, based on a determination of a data dependency error for the given memory operation, rollback execution of the instructions and repeat execution of the given memory operation in an in-order manner.

8. A method comprising, within a processor:
receiving an instruction stream, the instruction stream previously reordered by a software scheduler and including a plurality of memory operations, each of the plurality of memory operations associated with a set of alias information, the alias information indicating how a given memory operation may be evaluated;
reordering, in hardware, the instruction stream for out-of-order execution by resources of the processor;
executing the instruction stream out-of-order;
determining, for the given memory operation and based upon the set of alias information, a checking range of memory atoms subsequent to the given memory operation in the instruction stream and a virtual order of the memory operation, the virtual order indicating an original ordering of instructions before reordering by the software scheduler;
reordering, after execution and before retirement of instructions of the instruction stream, the instruction stream according to an order as received;
determining whether the reordering of the instruction stream in hardware and subsequent execution caused a data dependency error; and
determine, based upon the checking range and the virtual order, whether the reordering of the instruction stream by the software scheduler and subsequent execution caused a data dependency error for the given memory operation when compared to the memory atoms.

9. The method of claim 8 , wherein:
the alias information includes a high offset; and
further comprising evaluating memory atoms that are ordered past the given memory operation plus the high offset, wherein the memory atoms have executed before the given memory operation.

10. The method of claim 9 , wherein the virtual order indicating an original ordering of the instructions before reordering by the software scheduler is based upon a memory identification of the given memory operation and the high offset.

11. The method of claim 8 , wherein:
the alias information includes a low offset; and
further comprising evaluating memory atoms that are ordered between the given memory operation and the given memory operation plus the low offset, wherein the memory atoms have executed after the given memory operation.

12. The method of claim 8 , further comprising:
evaluating the given memory operation against the range of memory atoms with respect to a first set of criteria;
disregarding elements of the range of memory atoms that indicate that comparison of a given memory atom with the given memory operation cannot produce a data dependency error; and
selectively evaluating the given memory operation against remaining elements of the range of memory atoms with respect to a second set of criteria.

13. The method of claim 8 , wherein:
the alias information includes a high offset and a low offset; and
further comprising:
evaluating memory atoms that are ordered past the given memory operation plus the high offset, wherein the memory atoms have executed before the given memory operation;
evaluating memory atoms that are ordered between the given memory operation and the given memory operation plus the low offset, wherein the memory atoms have executed after the given memory operation; and
evaluating memory atoms that are ordered between the low offset and the high offset regardless of execution order.

14. A system comprising:
an interface including circuitry to receive an instruction stream as reordered by a software scheduler, each of a plurality of memory operations associated with a set of alias information; and
a processor communicatively coupled to the interface and to execute the instruction stream, including:
a hardware scheduler including circuitry to reorder, in hardware, the instruction stream for out-of-order execution by resources of the processor;
a calculation module including circuitry to determine, for a given memory operation and based upon the set of alias information, a check range of memory atoms subsequent to the given memory operation in the instructi

Assignees

• Theur Rainer
• Raman Arun
• Topp Jaroslaw
• Ranjan Rakesh
• Winkel Sebastian
• Stellpflug Gregor
• Bretthauer Ulrich
• Intel Corp

Inventors

• Theur Rainer
• Raman Arun
• Topp Jaroslaw
• Ranjan Rakesh
• Winkel Sebastian
• Stellpflug Gregor
• Bretthauer Ulrich

Classifications

• G06F9/3855 Primary

  Physics · mapped topic

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/3856 Primary

  Reordering of instructions, e.g. using queues or age tags · CPC title