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US-2024311371-A1 · Sep 19, 2024 · US
Computing device with asynchronous auxiliary execution unit
US9201801B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9201801-B2 |
| Application number | US-88243410-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 15, 2010 |
| Priority date | Sep 15, 2010 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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Abstract
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A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.
First claim
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What is claimed is: 1. A computing device comprising: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute said primary execution unit instructions from said instruction cache; an auxiliary execution unit configured to receive and execute only said auxiliary execution unit instructions from said instruction cache in a manner independent from a…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9201801B2 cover?
- A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions fr…
- Who is the assignee on this patent?
- Boury Bechara F, Mitchell Michael Bryan, Steinmetz Paul Michael, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0875. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).