Solid-state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9521350-B2
Application number	US-201514983111-A
Country	US
Kind code	B2
Filing date	Dec 29, 2015
Priority date	Jan 28, 2010
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

First claim

What is claimed is:

1. An imaging device comprising:
a first shared pixel including:
a first plurality of photoelectric conversion portions, and
a first floating diffusion;

a second shared pixel disposed adjacent to the first shared pixel and including:
a second plurality of photoelectric conversion portions, and
a second floating diffusion; and

a transistor portion, the transistor portion including a first reset transistor, a second reset transistor, and an amplification transistor,
wherein a gate terminal of the amplification transistor is disposed in a first row located between the first shared pixel and the second shared pixel, and
wherein a gate terminal of the first reset transistor and a gate terminal of the second reset transistor are disposed separated from one another in a second row.

2. The imaging device according to claim 1 , wherein the first shared pixel or the second shared pixel is disposed between the first row and the second row.

3. The imaging device according to claim 1 , wherein the transistor portion further includes a selection transistor, wherein a gate terminal of the selection transistor is disposed in the first row.

4. The imaging device according to claim 1 , wherein the first shared pixel further includes a first transfer transistor disposed between the first plurality of photoelectric conversion portions and the first floating diffusion, and the second shared pixel further includes a second transfer transistor disposed between the second plurality of photoelectric conversion portions and the second floating diffusion.

5. The imaging device according to claim 1 , wherein the first plurality of photoelectric conversion portions includes four photoelectric conversion portions, and the second plurality of photoelectric conversion portions includes four photoelectric conversion portions.

6. The imaging device according to claim 1 , wherein the first reset transistor and the second reset transistor are connected to a power source line at a connection point located between the gate terminal of the first reset transistor and the gate terminal of the second reset transistor.

7. The imaging device according to claim 6 , wherein the first reset transistor and the second reset transistor share a common drain terminal, and the common drain terminal is disposed between the gate terminal of the first reset transistor and the gate terminal of the second reset transistor.

8. The imaging device according to claim 6 , wherein the connection point is located at the common drain terminal.

9. The imaging device according to claim 1 , further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the first side of the semiconductor substrate.

10. The imaging device according to claim 1 , further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the second side of the semiconductor substrate.

11. An electronic apparatus comprising:
an imaging device;
an optical system configured to guide incident light to the imaging device; and
a signal processing circuit configured to process an output signal of the imaging device,
wherein the imaging device includes:
a first shared pixel including:
a first plurality of photoelectric conversion portions, and
a first floating diffusion;

a second shared pixel disposed adjacent to the first shared pixel and including:
a second plurality of photoelectric conversion portions, and

a second floating diffusion; and
a transistor portion, the transistor portion including a first reset transistor, a second reset transistor, and an amplification transistor,

wherein a gate terminal of the amplification transistor is disposed in a first row located between the first shared pixel and the second shared pixel, and
wherein a gate terminal of the first reset transistor and a gate terminal of the second reset transistor are disposed separated from one another in a second row.

12. The electronic apparatus according to claim 11 , wherein the first shared pixel or the second shared pixel is disposed between the first row and the second row.

13. The electronic apparatus according to claim 11 , wherein the transistor portion further includes a selection transistor, wherein a gate terminal of the selection transistor is disposed in the first row.

14. The electronic apparatus according to claim 11 , wherein the first shared pixel further includes a first transfer transistor disposed between the first plurality of photoelectric conversion portions and the first floating diffusion, and the second shared pixel further includes a second transfer transistor disposed between the second plurality of photoelectric conversion portions and the second floating diffusion.

15. The electronic apparatus according to claim 11 , wherein the first plurality of photoelectric conversion portions includes four photoelectric conversion portions, and the second plurality of photoelectric conversion portions includes four photoelectric conversion portions.

16. The electronic apparatus according to claim 11 , wherein the first reset transistor and the second reset transistor are connected to a power source line at a connection point located between the gate terminal of the first reset transistor and the gate terminal of the second reset transistor.

17. The electronic apparatus according to claim 16 , wherein the first reset transistor and the second reset transistor share a common drain terminal, and the common drain terminal is disposed between the gate terminal of the first reset transistor and the gate terminal of the second reset transistor.

18. The electronic apparatus according to claim 16 , wherein the connection point is located at the common drain terminal.

19. The electronic apparatus according to claim 11 , further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the first side of the semiconductor substrate.

20. The electronic apparatus according to claim 11 , further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the second side of the semiconductor substrate.

Assignees

• Sony Corp

Inventors

• Kido Hideo
• Yamamoto Atsuhiko
• Yamada Akihiro

Classifications

• H04N25/767 Primary

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title