Solid-state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9270915-B2
Application number	US-201514796599-A
Country	US
Kind code	B2
Filing date	Jul 10, 2015
Priority date	Jan 28, 2010
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

First claim

What is claimed is:

1. An imaging device comprising:
a first shared pixel including:
a first plurality of photoelectric conversion portions, and
a first transistor portion shared by the first plurality of photoelectric conversion portions, the first transistor portion including a first reset transistor, a first amplification transistor, and a first selection transistor; and
a second shared pixel disposed adjacent to the first shared pixel and including:
a second plurality of photoelectric conversion portions, and
a second transistor portion shared by the second plurality of photoelectric conversion portions, the second transistor portion including a second reset transistor, a second amplification transistor, and a second selection transistor,
wherein a gate terminal of the first selection transistor, a gate terminal of the first amplification transistor, a gate terminal of the second amplification transistor, and a gate terminal of the second selection transistor are adjacent one another in a first row in this order, and
wherein a gate terminal of the first reset transistor and a gate terminal of the second reset transistor are disposed in a second row.

2. The imaging device according to claim 1 , wherein
the first plurality of photoelectric conversion portions includes a first photoelectric conversion portion and a second photoelectric conversion portion, and
the second plurality of photoelectric conversion portions includes a third photoelectric conversion portion and a fourth photoelectric conversion portion.

3. The imaging device according to claim 2 , wherein
the first photoelectric conversion portion and the third photoelectric conversion portion are disposed in a third row, and
the third row is disposed between the first row and the second row.

4. The imaging device according to claim 2 , wherein
the first shared pixel includes a first floating diffusion shared by the first photoelectric conversion portion and the second photoelectric conversion portion, and
the second shared pixel includes a second floating diffusion shared by the third photoelectric conversion portion and the fourth photoelectric conversion portion.

5. The imaging device according to claim 4 , wherein
the first floating diffusion is connected to the first amplification transistor and the first reset transistor, and
the second floating diffusion is connected to the second amplification transistor and the second reset transistor.

6. The imaging device according to claim 4 , wherein
the first floating diffusion is connected to the first amplification transistor and the first reset transistor via a first floating diffusion line extending in a vertical direction, and
the second floating diffusion is connected to the second amplification transistor and the second reset transistor via a second floating diffusion line extending in the vertical direction.

7. The imaging device according to claim 1 , wherein
the first selection transistor is connected to a first vertical signal line at a first signal connection point,
the second selection transistor is connected to a second vertical signal line at a second signal connection point, and
the gate terminal of the first amplification transistor and the gate terminal of the second amplification transistor are disposed between the first signal connection point and the second signal connection point in the first row.

8. The imaging device according to claim 1 , wherein
the first amplification transistor is connected to a power source line at a power connection point, and
the power connection point is disposed between the gate terminal of the first amplification transistor and the gate terminal of the second amplification transistor in the first row.

9. The imaging device according to claim 8 , wherein the second amplification transistor is connected to the power source line at the power connection point.

10. The imaging device according to claim 1 , further comprising:
a peripheral circuit portion including a vertical driving circuit, at least one column signal processing circuit, a horizontal driving circuit, an output circuit, and a control circuit.

11. The imaging device according to claim 10 , wherein the control circuit is configured
to generate a clock signal or a control signal according to a vertical synchronization signal, a horizontal synchronization signal, and a master clock; and
to provide the clock signal or the control signal to the vertical driving circuit, the at least one column signal processing circuit, and/or the horizontal driving circuit.

12. The imaging device according to claim 10 , wherein the vertical driving circuit is configured to drive the first shared pixel and the second shared pixel in row units.

13. The imaging device according to claim 10 , wherein the at least one column signal processing circuit includes a first column signal processing circuit connected to the first shared pixel, and a second column signal processing circuit connected to the second shared pixel.

14. The imaging device according to claim 13 , wherein the horizontal driving circuit is configured to sequentially select the first column signal processing circuit and the second column signal processing circuit, and to output a respective pixel signal from the corresponding column processing circuit to a corresponding horizontal signal line.

15. The imaging device according to claim 10 , wherein the output circuit is configured to perform signal processing on a respective signal supplied from the at least one column signal processing circuit, and to output the respective processed signal.

16. The imaging device according to claim 1 , further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the first side of the semiconductor substrate.

17. The imaging device according to claim 1 , further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the second side of the semiconductor substrate.

18. An electronic apparatus comprising:
an imaging device;
an optical system configured to guide incident light to the imaging device; and
a signal processing circuit configured to process an output signal of the imaging device,
wherein the imaging device includes:
a first shared pixel including:
a first plurality of photoelectric conversion portions, and
a first transistor portion shared by the first plurality of photoelectric conversion portions, the first transistor portion including a first reset transistor, a first amplification transistor, and a first selection transistor; and

a second shared pixel disposed adjacent to the first shared pixel and including:
a second plurality of photoelectric conversion portions, and
a second transistor portion shared by the second plurality of photoelectric conversion portions, the second transistor portion including a second reset transistor, a second amplification transistor, and a second selection transistor,

wherein a gate terminal of the first selection transistor, a gate terminal of the first amplifica

Assignees

• Sony Corp

Inventors

• Kido Hideo
• Yamamoto Atsuhiko
• Yamada Akihiro

Classifications

• H04N25/767 Primary

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title