Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9520499-B2
Application number	US-201514867423-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	May 30, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a lower surface that extends in a first direction and in a second direction that is perpendicular to the first direction;
first and second active fins that project upwardly from an upper surface of the substrate in a third direction that is perpendicular to both the first and second directions, the first and second active fins extending in the first direction and being spaced apart from each other along the second direction;
a field insulating film on the upper surface of the substrate between the first and second active fins; and
a first gate structure on an upper surface of the field insulating film, the first gate structure extending in the second direction to cross the first and second active fins,
wherein the field insulating film includes a first recessed region adjacent the first active fin, a second recessed region adjacent the second active fin, and a third region that is between the first and second recessed regions, the third region having a thickness in the third direction that exceeds the average thicknesses in the third direction of the respective first and second recessed regions, and
wherein a first length of the first recessed region in the second direction is less than a third length of the third region in the second direction and a second length of the second recessed region in the second direction is less than the third length of the third region in the second direction,
wherein a width of a lower portion of the first active fin in the second direction is greater than or equal to a width of an upper portion of the first active fin in the second direction, a width of a lower portion of the second active fin in the second direction is greater than or equal to a width of an upper portion of the second active fin in the second direction, and the first gate structure directly contacts sidewalls of the first and second active fins.

2. The semiconductor device of claim 1 , wherein the third length of the third region in the second direction exceeds a length of the first active fin in the second direction.

3. The semiconductor device of claim 1 , wherein the third region has a substantially flat upper surface, and wherein the first gate structure includes a first metal gate.

4. The semiconductor device of claim 1 , the semiconductor device further comprising a second gate structure on the upper surface of the substrate, the second gate structure extending in the second direction to cross the first and second active fins, the second gate structure being spaced apart from the first gate structure along the first direction, wherein the first and second gate structures include respective first and second metal gates.

5. The semiconductor device of claim 4 , further comprising a dummy metal gate that extends in the second direction to cross end portions of the first and second active fins, a portion of the dummy metal gate that is between the first and second active fins having a different shape than a portion of the first gate structure that is between the first and second active fins.

6. The semiconductor device of claim 3 , further comprising a spacer on opposed sides of the first gate structure.

7. The semiconductor device of claim 6 , wherein the first gate structure includes a gate insulating film that extends upwardly along respective inner sidewalls of the spacer between each inner sidewall of the spacer and a metal gate of the first gate structure.

8. The semiconductor device of claim 3 , wherein a first portion of the first gate structure that is above the first recessed region of the gate insulating film has a first thickness in the third direction, a second portion of the first gate structure that is above the second recessed region of the gate insulating film has a second thickness in the third direction and a third portion of the first gate structure that is above the third region of the gate insulating film has a third thickness that exceeds the first thickness and the second thickness.

9. The semiconductor device of claim 6 , further comprising a source region in the first active fin on a first side of the first gate structure and a drain region in the first active fin on a second, opposite side of the first gate structure, wherein upper surfaces of the source region and the drain region are on respective sidewalls of the spacer.

10. A semiconductor device comprising:
first and second active fins that project from a substrate in a first direction;
a field insulating film on an upper surface of the substrate between the first and second active fins;
a metal gate structure on the field insulating film that crosses over the first and second active fins, the metal gate structure on upper surfaces and opposed sidewalls of the first and second active fins; and
a spacer on at least one side of the metal gate structure,
wherein the field insulating film includes a first recessed region that is adjacent the first active fin that has a first minimum thickness, and a second region that is spaced apart from the first active fin and from the second active fin that has a second thickness that exceeds the first minimum thickness, and
wherein the metal gate structure includes a gate insulating film extending in the first direction along side walls of the spacer,
wherein the metal gate structure extends in a second direction, and wherein a length of the second region of the field insulating film in the second direction exceeds a length of the first active fin in the second direction and exceeds a length of the first recessed region of the field insulating film in the second direction,
wherein the first active fin extends in a third direction that is perpendicular to the first and second directions, the semiconductor device further comprising a dummy metal gate that is disposed at an end portion of the first active fin.

11. The semiconductor device of claim 10 , wherein the metal gate structure disposed above the first recessed region of the gate insulating film has a maximum thickness that exceeds a thickness of the metal gate structure that is disposed above the second region of the gate insulating film.

12. The semiconductor device of claim 10 , wherein a width of a lower portion of the first active fin in the second direction is greater than or equal to a width of an upper portion of the first active fin in the second direction, a width of a lower portion of the second active fin in the second direction is greater than or equal to a width of an upper portion of the second active fin in the second direction, and the field insulating film directly contacts sidewalls of the first and second active fins.

13. The semiconductor device of claim 10 , wherein a shape of the metal gate structure and a shape of the dummy metal gate are different from each other.

14. The semiconductor device of claim 10 , wherein the metal gate structure comprises a first metal gate structure, the semiconductor device further comprising a second metal gate structure on the upper surface of the substrate, the second metal gate structure extending in the second direction to cross the first and second active fins, the second metal gate structure being spaced apart from the first metal gate structure along a third direction that is perpendicular to the second direction.

15. The semiconductor device of claim 10 , further comprising a source region and a drain region formed at the first active fin on opposite sides of the metal gate structure, upper surfaces of the source region and the drain region are higher above a lower surface of the substrate than is a lower s

Assignees

• Kim Sung-Min
• Kang Ji-Su
• Lee Dong-Kyu
• Cha Dong-Ho
• Samsung Electronics Co Ltd

Inventors

• Kim Sung-Min
• Kang Ji-Su
• Lee Dong-Kyu
• Cha Dong-Ho

Classifications

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title