Semiconductor devices including a stressor in a recess and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9520497-B2
Application number	US-201514951932-A
Country	US
Kind code	B2
Filing date	Nov 25, 2015
Priority date	Nov 22, 2012
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a gate structure on the substrate;
a spacer adjacent to a sidewall of the gate structure; and
a semiconductor layer disposed adjacent to the sidewall of the gate structure and disposed in a recess that extends below an upper surface of the substrate, the semiconductor layer being a strain-inducing pattern,
wherein a portion of the recess underlies the gate structure,
wherein the semiconductor layer comprises a portion that is in the substrate and directly contacts a lower surface of the spacer, and an interface between the spacer and the portion of the semiconductor layer is not below a lower surface of the gate structure, and
wherein the portion of the semiconductor layer comprises a first sidewall that has a linear shape and directly contacts the lower surface of the spacer, and the first sidewall of the portion of the semiconductor layer forms an acute angle with the lower surface of the spacer and extends beyond the sidewall of the gate structure.

2. The semiconductor device of claim 1 , wherein the interface between the spacer and the portion of the semiconductor layer is coplanar with the lower surface of the gate structure.

3. The semiconductor device of claim 1 , wherein the gate structure includes a gate dielectric and a gate electrode over the gate dielectric.

4. The semiconductor device of claim 1 , wherein the gate structure comprises a gate electrode, a first gate dielectric layer, and a second gate dielectric layer comprising a high-K dielectric material, and
the portion of the recess underlies the gate electrode, the first gate dielectric layer or the second gate dielectric layer.

5. The semiconductor device of claim 1 , wherein the portion of the semiconductor layer comprises a second sidewall that has a linear shape and directly contacts the first sidewall of the portion of the semiconductor layer,
wherein the first sidewall and the second sidewall converge at a convergence interface, and
wherein the gate structure overlaps the convergence interface.

6. The semiconductor device of claim 3 , wherein the spacer contacts the gate electrode.

7. The semiconductor device of claim 3 , further comprising at least one nitride layer between the spacer and the gate electrode.

8. The semiconductor device of claim 3 , wherein the gate structure includes a high-K dielectric material.

9. The semiconductor device of claim 5 , further comprising a lightly doped drain (LDD) region in the substrate, wherein the convergence interface directly contacts the LDD region.

10. The semiconductor device of claim 5 , wherein the portion of the semiconductor layer is spaced apart from the lower surface of the gate structure, and
wherein a distance between the lower surface of the gate structure and the convergence interface is from 3 nm to 7 nm.

11. The semiconductor device of claim 8 , wherein the spacer contacts the gate electrode.

12. The semiconductor device of claim 8 , further comprising at least one nitride layer between the spacer and the gate electrode.

13. The semiconductor device of claim 9 , wherein the LDD region comprises a first impurity having a p-conductivity type and phosphorous (P).

14. The semiconductor device of claim 9 , wherein the LDD region comprises a first impurity having a p-conductivity type, and the spacer comprises a second impurity having an n-conductivity type.

15. The semiconductor device of claim 13 , wherein a phosphorous concentration in the LDD region is in a range of from 5E18 to 1E19 atoms/cm 3 .

16. A semiconductor device comprising:
a substrate;
a gate structure including a gate dielectric layer over the substrate and a gate electrode over the gate dielectric layer;
a spacer adjacent to a sidewall of the gate electrode; and
a semiconductor layer disposed adjacent to the gate structure and disposed in a recess that extends below an upper surface of the substrate, the semiconductor layer being a strain-inducing pattern,
wherein a portion of the recess underlies the gate structure,
wherein the spacer directly contacts a first portion of the semiconductor layer above a lower surface of the gate dielectric layer,
wherein the semiconductor layer comprises a second portion in the substrate, and the second portion of the semiconductor layer comprises a first sidewall that directly contacts the upper surface of the substrate and has a linear shape and a second sidewall that directly contacts the first sidewall and has a linear shape,
wherein the first and second sidewalls of the second portion of the semiconductor layer are slanted with respect to the upper surface of the substrate and converge at a convergence interface, and
wherein the gate electrode overlaps the convergence interface.

17. The semiconductor device of claim 16 , wherein an interface between the spacer and the semiconductor layer located under the spacer is not below a lower surface of the gate structure.

18. The semiconductor device of claim 16 , wherein the first and second sidewalls of the second portion of the semiconductor layer are in the same crystal plane.

19. The semiconductor device of claim 16 , further comprising a lightly doped drain (LDD) region in the substrate, wherein the LDD region comprises a first impurity having a p-conductivity type and phosphorous (P).

20. The semiconductor device of claim 19 , wherein the convergence interface directly contacts the LDD region.

21. A method for forming a semiconductor device, the method comprising:
forming a gate structure over a semiconductor substrate, the gate structure including a gate insulating layer and a gate electrode over the gate insulating layer;
forming a first spacer over the semiconductor substrate;
forming a second spacer along a sidewall of the gate structure;
forming a recess extending into the semiconductor substrate adjacent to the gate structure, wherein the recess comprises a notched portion of the semiconductor substrate that underlies the gate structure and is spaced apart from the gate structure, the notched portion comprises a first sidewall directly contacting an upper surface of the semiconductor substrate and a second sidewall directly contacting the first sidewall of the recess, each of the first and second sidewalls has a linear shape, and the gate electrode overlaps a portion of the recess;
removing at least a portion of the first spacer; and
filling the recess with a stressor that directly contacts a bottom surface of the first spacer,
wherein a contacting interface between the stressor and the bottom surface of the first spacer is not below a lower surface of the gate insulating layer, and
the stressor is a strain-inducing pattern.

22. The method of claim 21 , wherein the forming the recess includes performing an anisotropic etch process, whereby the recess extends under the first spacer.

23. The method of claim 21 , further comprising forming a nitride layer along the sidewall of the gate structure.

24. The method of claim 21 , wherein the first sidewall and the second sidewall of the recess converge at a convergence interface, and
wherein a distance between the lower surface of the gate insulating layer and the convergence interface is from 3 nm to 7 nm.

25. The method of claim 21 , further comprising forming a lightly doped drain (LDD) region in the substrate before forming the recess, wherein the first sidewall and the second sid

Assignees

• Shin Dong-Suk
• Lee Chul-Woong
• Chung Hoi-Sung
• Kim Young-Tak
• Lee Nae-In
• Samsung Electronics Co Ltd

Inventors

• Shin Dong-Suk
• Lee Chul-Woong
• Chung Hoi-Sung
• Kim Young-Tak
• Lee Nae-In

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/797 Primary

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title