Adaptive erase of a storage device

Patent metadata

Field	Value
Publication number	US-9520197-B2
Application number	US-201314135260-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Nov 22, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

The various implementations described herein include systems, methods and/or devices used to enable adaptive erasure in a storage device. The method includes performing a plurality of memory operations including read operations and respective erase operations on portions of one or more non-volatile memory devices specified by the read operations and respective erase operations, where the respective erase operations are performed using a first set of erase parameters that has been established as a current set of erase parameters prior to performing the respective erase operations. The method includes, in accordance with each erase operation of at least a subset of the respective erase operations, updating one or more erase statistics that correspond to performance of multiple erase operations. The method includes, in accordance with a comparison of the erase statistics with an erasure performance threshold, establishing a second set of erase parameters as the current set of erase parameters.

First claim

What is claimed is:

1. A method of erasing data in a storage device, the storage device having one or more non-volatile memory devices, the method comprising:
performing a plurality of memory operations including read operations and a first set of erase operations on portions of the one or more non-volatile memory devices specified by the read operations and the first set of erase operations, wherein the first set of erase operations are performed using a first set of erase parameters that has been established as a current set of erase parameters prior to performing the first set of erase operations;
in accordance with each erase operation of at least a subset of the first set of erase operations, updating one or more erase statistics that correspond to performance of multiple erase operations;
in accordance with a comparison of the erase statistics with an erasure performance threshold, establishing a second set of erase parameters as the current set of erase parameters; and
subsequent to establishing the second set of erase parameters as the current set of erase parameters, performing a subsequent erase operation on one or more portions of the one or more non-volatile memory devices using the second set of erase parameters;
wherein
the method includes generating a count of how many erase operations of the multiple erase operations have durations that exceed a predefined duration threshold, wherein each erase operation erases one or more blocks of memory cells; and
a respective erase statistic of the erase statistics corresponds to the count of how many erase operations of the multiple erase operations have durations that exceed the predefined duration threshold.

2. The method of claim 1 , wherein the one or more erase statistics include erase operation duration statistics with respect to durations for the multiple erase operations.

3. The method of claim 1 , including, for each erase operation of the first set of erase operations, updating the one or more erase statistics.

4. The method of claim 1 , wherein updating the one or more erase statistics that correspond to the performance of the multiple erase operations includes identifying erase operations, of the multiple erase operations, whose durations exceed a predefined duration threshold, and updating at least one of the one or more erase statistics in accordance with the identified erase operations.

5. The method of claim 1 , wherein the first set of erase parameters includes an initial pulse voltage and an incremental pulse voltage.

6. The method of claim 1 , including, in accordance with a determination that one or more of the erase statistics correspond to a rate or count of successful erase operations that equals or exceeds an erasure success threshold, establishing the second set of erase parameters as the current set of erase parameters by decreasing one or both of: an initial pulse voltage and an incremental pulse voltage of the current set of erase parameters.

7. The method of claim 1 , including, in accordance with a determination that one or more of the erase statistics correspond to a rate or count of unsuccessful erase operations that equals or exceeds an erasure failure threshold, establishing the second set of erase parameters as the current set of erase parameters by increasing one or both of: an initial pulse voltage and an incremental pulse voltage of the current set of erase parameters.

8. The method of claim 1 , wherein each erase operation of the first set of erase operations includes:
applying a first voltage pulse to one or more portions of the one or more non-volatile memory devices in accordance with the current set of erase parameters; and,
in accordance with a determination that the one or more portions of the one or more non-volatile memory devices have not been successfully erased, applying one or more subsequent voltage pulses in accordance with the current set of erase parameters until predefined criteria have been met, the predefined criteria including that the one or more portions of the one or more non-volatile memory devices have been successfully erased.

9. The method of claim 1 , wherein each erase operation of the first set of erase operations includes:
applying a set of voltage pulses to one or more portions of the one or more non-volatile memory devices in accordance with the current set of erase parameters; and,
in accordance with a determination that the one or more portions of the one or more non-volatile memory devices have not been successfully erased, applying one or more subsequent sets of voltage pulses to the one or more portions of the one or more non-volatile memory devices until second predefined criteria have been met, the second predefined criteria including that the one or more portions of the one or more non-volatile memory devices have been successfully erased.

10. The method of claim 9 , further comprising:
receiving one or more host read commands to read data from one or more memory blocks on the storage device; and,
prior to applying the one or more subsequent sets of voltage pulses to the one or more portions of the one or more non-volatile memory devices, processing at least a subset of the one or more host read commands to read data from the one or more memory blocks on the storage device.

11. The method of claim 1 , further comprising:
identifying one or more portions of the one or more non-volatile memory devices that fail to satisfy a predefined erasure performance requirement when one or more erase operations are performed using the first set of erase parameters;
subsequent to identifying the one or more portions of the one or more non-volatile memory devices, forgoing erase operations on the one or more portions of the one or more non-volatile memory devices using the first set of erase parameters; and,
subsequent to establishing the second set of erase parameters as the current set of erase parameters, performing the subsequent erase operation on at least a subset of the identified one or more portions of the one or more non-volatile memory devices using the second set of erase parameters.

12. The method of claim 1 , wherein the method is performed by a non-volatile memory controller of the storage device and the one or more erase statistics correspond to performance of multiple erase operations on portions of one or more non-volatile memory devices coupled to the non-volatile memory controller.

13. The method of claim 1 , wherein the storage device comprises a plurality of non-volatile memory controllers, each coupled to a distinct set of one or more non-volatile memory devices in the storage device, and the method is performed independently by each non-volatile memory controller of the plurality of non-volatile memory controllers of the storage device.

14. The method of claim 1 , wherein the one or more non-volatile memory devices comprise one or more flash memory devices.

15. The method of claim 1 , wherein multiple sets of erase parameters, including the first set of erase parameters and the second set of erase parameters, are stored in non-volatile memory of the storage device.

16. A storage device, having one or more non-volatile memory devices, comprising:
an interface for coupling the storage device to a host system; and
one or more controllers, each of the one or more controllers configured to:
perform a plurality of memory operations including read operations and a first set of erase operations on portions of the one or more non-volatile memory devices specified by the read operations and the first set of erase operations, wherein the first set of erase

Assignees

• Sandisk Entpr Ip Llc
• Sandisk Technologies Llc

Inventors

• Fitzpatrick James
• Higgins James
• Li Li
• Wongso Mervyn

Classifications

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/344

  Arrangements for verifying correct erasure or for detecting overerased cells · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title