Resistive memory write operation with merged reset

Patent metadata

Field	Value
Publication number	US-9520192-B2
Application number	US-201414320609-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

In a memory device where writing a memory cell to a first bit state takes longer than writing to the second bit state, selectively executing the write operation can amortize the performance cost of writing the bit state that takes longer to write. Write logic dequeues multiple cachelines from a write buffer and sets all bits of all cachelines to the first bit state in a single write operation. The write logic then executes separate write operations on each cacheline separately to selectively write memory cells of each respective cacheline to the second bit state.

First claim

What is claimed is:

1. A method for writing a memory device, comprising:
dequeuing a number greater than one of cachelines to perform write operations in a memory device, wherein each cacheline includes a row of memory cells, each memory cell controlled by three separate control lines, wherein writing to a first memory cell state takes longer than writing to a second memory cell state;
setting all of the memory cells of the number of cachelines to the first memory cell state in a single write operation; and
executing write operations to the number of cachelines individually to selectively write memory cells of the respective cachelines to the second memory cell state.

2. The method of claim 1 , wherein the first memory cell state is zero, and the second memory cell state is one.

3. The method of claim 1 , wherein the memory device comprises a magnetoresistive memory device.

4. The method of claim 3 , wherein the memory device comprises a spin transfer torque (STT) memory device.

5. The method of claim 1 , wherein dequeuing the number of cachelines further comprises:
dynamically selecting the number of cachelines to dequeue.

6. The method of claim 5 , wherein dynamically selecting the number of cachelines to dequeue further comprises:
determining how much current is available in the memory device to perform the single write operation; and
selecting a maximum number of cachelines within a limit of how much current is available.

7. The method of claim 1 , wherein dequeuing the number of cachelines further comprises:
dequeuing from one of two write buffers, wherein one buffer is designated as filled and the other buffer is designated as being filled, wherein the buffers rotate designations based on when the buffer being filled becomes full.

8. A memory circuit for performing a write operation with a multi-cacheline reset operation, the memory circuit comprising:
a memory cell array managed as multiple cachelines, wherein each cacheline includes a row of memory cells, each memory cell to be controlled by three separate control lines, wherein a write of a memory cell to a first memory cell state takes longer than a write of the memory cell to a second memory cell state;
a write buffer to hold data to write to the multiple cachelines; and
write logic to dequeue a number greater than one of cachelines to perform write operations, set all of the memory cells of the number of cachelines to the first memory cell state in a single write operation, and execute write operations to the number of cachelines individually to selectively write memory cells of the respective cachelines to the second memory cell state.

9. The memory circuit of claim 8 , wherein the first memory cell state is zero, and the second memory cell state is one.

10. The memory circuit of claim 8 , wherein the memory circuit comprises a magnetoresistive memory circuit.

11. The memory circuit of claim 10 , wherein the memory circuit comprises a spin transfer torque (STT) memory circuit.

12. The memory circuit of claim 8 , wherein the write logic is further to dynamically select the number of cachelines to dequeue.

13. The memory circuit of claim 12 , wherein the write logic is to dynamically select the number of cachelines to dequeue including
to determine how much current is available in the memory circuit to perform the single write operation; and
to select a maximum number of cachelines within a limit of how much current is available.

14. The memory circuit of claim 8 , wherein the write buffer comprises two separate buffers, a first buffer to queue new write commands, and a second buffer to be dequeued for the single write operation, wherein the two buffers switch based on the second buffer becoming empty.

15. A system comprising:
a memory circuit including
a memory cell array managed as multiple cachelines, wherein each cacheline includes a row of memory cells, each memory cell to be controlled by three separate control lines, wherein a write of a memory cell to a first memory cell state takes longer than a write of the memory cell to a second memory cell state;
a write buffer to hold data to write to the multiple cachelines; and
write logic to dequeue a number greater than one of cachelines to perform write operations, set all of the memory cells of the number of cachelines to the first memory cell state in a single write operation, and execute write operations to the number of cachelines individually to selectively write memory cells of the respective cachelines to the second memory cell state; and

a touchscreen display coupled to generate a display based on data accessed from the memory circuit.

16. The system of claim 15 , wherein the first memory cell state is zero, and the second memory cell state is one.

17. The system of claim 15 , wherein the memory circuit comprises a spin transfer torque (STT) memory circuit.

18. The system of claim 15 , wherein the write logic is further to dynamically select the number of cachelines to dequeue.

19. The system of claim 18 , wherein the write logic is to dynamically select the number of cachelines to dequeue including
to determine how much current is available in the memory circuit to perform the single write operation; and
to select a maximum number of cachelines within a limit of how much current is available.

20. The system of claim 15 , wherein the write buffer comprises two separate buffers, a first buffer to queue new write commands, and a second buffer to be dequeued for the single write operation, wherein the two buffers switch based on the second buffer becoming empty.

Assignees

• Naeimi Helia
• Lu Shih-Lien L
• Augustine Charles
• Intel Corp

Inventors

• Naeimi Helia
• Lu Shih-Lien L
• Augustine Charles

Classifications

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C14/0036 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G11C14/0081

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title