Asynchronous FIFO memory with read and write counter circuitry

Patent metadata

Field	Value
Publication number	US-9520179-B1
Application number	US-201615205914-A
Country	US
Kind code	B1
Filing date	Jul 8, 2016
Priority date	Jul 8, 2016
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A read count circuit and a write count circuit, each for providing a count of data read from or written to, respectively, an asynchronous FIFO memory device. These circuits use read/write clock and read/write enable inputs, the selection of which depend on whether a read or write count is being provided. Essentially, the circuit comprises a shift register having a number of cascaded flip-flops, where the number of flip-flops is based on a ratio of one clock frequency to the other. An AND element at the output of each flip-flop AND's the output of the associated flip-flop with a read/write enable signal. A pulse generator at the output of each AND element synchronizes the outputs of the AND elements with the read/write clock. An adder then sums the outputs of the pulse generators. A counter increments with the adder output and decrements with a read/write enable signal, upon each read/write clock signal, thereby providing a read/write count output.

First claim

What is claimed is:

1. A read count circuit for providing a count of data read from an asynchronous FIFO memory device, the FIFO memory device providing a read clock signal, a write clock signal, a read enable signal, and a write enable signal, with each of the clock signals having an associated clock frequency, the circuit comprising:
a shift register comprising a number of cascaded flip-flops, each flip-flop having the write clock signal as its clock input, and the data output of the preceding flip-flop as its data input, with the data output of the last flip-flop being the data input to the first flip-flop;
wherein the number of flip-flops is the size of a data vector whose size is based on a ratio of one clock frequency to the other;
an AND element at the output of each flip-flop, operable to AND the output of the associated flip-flop with the write enable signal;
a pulse generator at the output of each AND element, operable to synchronize the outputs of the AND elements with the read clock;
an adder operable to receive and sum the outputs of each pulse generator, thereby providing a write pulse sum; and
a counter operable to increment with the write pulse sum and to decrement with the read enable signal upon each read clock signal, thereby providing a read count output.

2. The read count circuit of claim 1 , wherein the read clock signal is faster than or the same speed as the write clock signal, and the size of the data vector is two.

3. The read count circuit of claim 1 , wherein each pulse generator comprises a series of flip-flops, the first flip-flop having the output of the associated AND element as its input, and the succeeding flip-flops having the read clock as their clock input.

4. A write count circuit for providing a count of data written to an asynchronous FIFO memory device, the FIFO memory device providing a read clock signal, a write clock signal, a read enable signal, and a write enable signal, with each of the clock signal having an associated frequency, the circuit comprising:
a shift register comprising a number of cascaded flip-flops, each flip-flop having the read clock signal as its clock input, and the data output of the preceding flip-flop as its data input, with the data output of the last flip-flop being the data input to the first flip-flop;
wherein the number of flip-flops is the size of a data vector whose size is based on a ratio of one clock frequency to the other;
an AND element at the output of each flip-flop, operable to AND the output of the associated flip-flop with the read enable signal;
a pulse generator at the output of each AND element, operable to synchronize the outputs of the AND elements with the write clock;
an adder operable to receive and sum the outputs of each pulse generator, thereby providing a read pulse sum; and
a counter operable to decrement with the read pulse sum and to increment with the write enable signal upon each write clock signal, thereby providing a write count output.

5. The write count circuit of claim 4 , wherein the write clock signal is faster than or the same speed as the read clock signal, and the size of the data vector is two.

6. The write count circuit of claim 4 , wherein each pulse generator comprises a series of flip-flops, the first flip-flop having the output of the associated AND element as its input, and the succeeding flip-flops having the write clock as their clock input.

Assignees

• Southwest Res Inst

Inventors

• Johnson Mark A

Classifications

• G06F5/12 Primary

  Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/106

  Data output latches · CPC title