Method of and device for processing data using a pipeline of processing blocks

Patent metadata

Field	Value
Publication number	US-9519486-B1
Application number	US-201213683720-A
Country	US
Kind code	B1
Filing date	Nov 21, 2012
Priority date	Nov 21, 2012
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A method of processing data in an integrated circuit is described. The method comprises establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data. A device for processing data in an integrated circuit is also described.

First claim

What is claimed is:

1. A method of processing data in an integrated circuit, the method comprising:
establishing a key-value store;
receiving data for a transaction at an input to a pipeline of processing blocks, wherein each processing block has a different function;
encoding state of the transaction as metadata that enables a subset of the processing blocks for processing the data;
passing the data and the metadata through the pipeline of processing blocks as a data packet having the data and the metadata; and
accessing the key-value store while processing the data in the subset of the processing blocks based upon the metadata.

2. The method of claim 1 wherein the metadata passes through the pipeline of processing blocks in a sub-channel or a sideband channel.

3. The method of claim 1 further comprising implementing a hash table to map a hash value to a unique memory address within the key-value store.

4. The method of claim 1 wherein accessing the key-value store while processing data in the subset of the processing blocks comprises updating the key-value store.

5. The method of claim 1 further comprising parsing data of the data packet based upon a transaction protocol.

6. The method of claim 5 further comprising formatting a response packet based upon the transaction protocol.

7. A device for processing data in an integrated circuit, the device comprising:
a network interface configured to receive data for a transaction;
a transaction protocol parser, coupled to the network interface, configured to encode state of the transaction as metadata that enables a subset of processing blocks in a pipeline of processing blocks for processing the data and to couple the data and the metadata to the pipeline of processing blocks as a data packet having the data and the metadata;
the pipeline of processing blocks coupled to the transaction protocol parser, wherein each processing block has a different function, and wherein the subset of the processing blocks processes the data based upon the metadata;
a key-value store coupled to the pipeline of processing blocks, wherein the pipeline of processing blocks accesses the key-value store while processing the data based upon the metadata.

8. The device of claim 7 wherein the key-value store comprises a plurality of memory locations each having a key and a corresponding value.

9. The device of claim 8 further comprising a hash table coupled to the pipeline of processing blocks, the hash table mapping a hash value to a unique memory address within the key-value store.

10. The device of claim 9 wherein the pipeline of processing blocks comprises a cache management circuit to maintain the hash table.

11. The device of claim 7 wherein the pipeline of processing blocks comprises an output block configured to format a response packet based upon the transaction protocol.

Assignees

• Xilinx Inc

Inventors

• Blott Michaela
• English Thomas B
• Vissers Kornelis A

Classifications

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• H03K19/17752 Primary

  for hot reconfiguration · CPC title

• G06F15/7878

  for pipeline reconfiguration · CPC title

• G06F9/3897

  with adaptable data path · CPC title

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title