Method for producing printed wiring board

US9516765B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9516765-B2
Application numberUS-201314065924-A
CountryUS
Kind codeB2
Filing dateOct 29, 2013
Priority dateNov 1, 2012
Publication dateDec 6, 2016
Grant dateDec 6, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for producing a printed wiring board which is capable of forming an insulating layer having a surface with low roughness and high adhesion strength to a conductive layer and of achieving an excellent performance in removal of smear, involves the following steps (A) to (F) in this order: (A) laminating, onto an internal layer circuit substrate, a resin sheet with a support which includes a support and a resin composition layer in contact with the support so that the resin composition layer is in contact with the internal layer circuit substrate; (B) thermally curing the resin composition layer of the resin sheet with a support to form an insulating layer; (C) perforating the insulating layer to form a via hole; (D) performing a desmear treatment; (E) peeling the support; and (F) forming a conductive layer on a surface of the insulating layer.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for producing a printed wiring board, comprising (A) to (F) in this order: (A) laminating, onto an internal layer circuit substrate, a resin sheet with a support which comprises a support and a resin composition layer in contact with the support, so that the resin composition layer is in contact with said internal layer circuit substrate; (B) thermally curing said resin composition layer of said resin sheet with a support to form an insulating layer; (C) perforating said insulating layer to form a via hole; (D) performing a desmear treatment; (E) peeling said support, to expose a surface of said insulating layer; and (F) forming a conductive layer on the surface of said insulating layer, wherein said resin composition layer of said resin sheet with a support comprises at least one epoxy resin, at least one curing agent, and at least one inorganic filler, said at least one curing agent comprises an active ester-based curing agent and a curing agent selected from the group consisting of a phenol-based curing agent and a naphthol-based curing agent, said at least one inorganic filler is treated with at least one surface treatment agent selected from the group consisting of an organosilazane compound, a titanate-based coupling agent, an aminosilane-based coupling agent, an epoxysilane-based coupling agent, and a mercaptosilane-based coupling agent, and said at least one inorganic filler is present in said resin composition layer in an amount of 72% by mass to 95% by mass, when a content of nonvolatile components in said resin composition layer is defined as 100% by mass. 2. A method for producing a printed wiring board according to claim 1 , wherein said desmear treatment (D) is a wet desmear treatment, a dry desmear treatment, or a combination thereof. 3. A method for producing a printed wiring board according to claim 1 , wherein said forming a conductive layer (F) comprises: performing a roughening treatment of the surface of said insulating layer, and wet plating said surface of the insulating layer to form said conductive layer, in this order. 4. A method for producing a printed wiring board according to claim 1 , wherein said forming a conductive layer (F) comprises: dry plating the surface of said insulating layer to form a metal layer, and wet plating a surface of said metal layer to form said conductive layer, in this order. 5. A method for producing a printed wiring board according to claim 1 , wherein said at least one inorganic filler has an average particle diameter of 0.01 μm to 3 μm. 6. A method for producing a printed wiring board according to claim 1 , wherein a surface of said at least one inorganic filler is treated with a surface treatment agent. 7. A printed wiring board, which is produced by the method according to claim 1 . 8. A semiconductor device, comprising a printed wiring board according to claim 7 . 9. A method for producing a printed wiring board according to claim 1 , wherein said forming a conductive layer (F) comprises: performing a roughening treatment of the surface of said insulating layer, the roughening treatment being selected from the group consisting of a dry sand blasting treatment, a wet sand blasting treatment and a desmear treatment using an oxidant solution. 10. A method for producing a printed wiring board according to claim 1 , wherein said forming a conductive layer (F) comprises: (a) performing a roughening treatment of the surface of said insulating layer, said roughening treatment being a wet roughening treatment or a dry roughening treatment selected from the group consisting of a dry sand blasting treatment and a plasma treatment, and wet plating said surface of said insulating layer, in this order, to form said conductive layer; or (b) dry plating the surface of said insulating layer to form a metal layer without performing a roughening treatment, and wet a plating surface of said metal layer, in this order, to form said conductive layer.

Assignees

Inventors

Classifications

  • Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor (other insulating materials H05K3/387) · CPC title

  • H05K3/465Primary

    by applying an insulating layer having channels for the next circuit layer · CPC title

  • Inorganic, non-metallic particles · CPC title

  • by forming conductive walled aperture in base · CPC title

  • by special treatment of the substrate · CPC title

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What does patent US9516765B2 cover?
A method for producing a printed wiring board which is capable of forming an insulating layer having a surface with low roughness and high adhesion strength to a conductive layer and of achieving an excellent performance in removal of smear, involves the following steps (A) to (F) in this order: (A) laminating, onto an internal layer circuit substrate, a resin sheet with a support which include…
Who is the assignee on this patent?
Ajinomoto Kk
What technology area does this patent fall under?
Primary CPC classification H05K3/465. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).