Wiring board and method for manufacturing same

US9516751B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9516751-B2
Application numberUS-201314417751-A
CountryUS
Kind codeB2
Filing dateMay 17, 2013
Priority dateSep 21, 2012
Publication dateDec 6, 2016
Grant dateDec 6, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10 . The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25 . Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction. The solder resist layer 25 includes, within the opening portion 43 , a side-surface covering portion 55 that covers the side surface of the connecting terminal portion 41 and a projecting wall portion 56 that is integrally formed with the side-surface covering portion 55 and disposed to project so as to intersect with the connection region 51.

First claim

Opening claim text (preview).

What is claimed is: 1. A wiring board, comprising a laminated body where respective one or more layers of insulating layers and conductor layers are laminated, the conductor layer in an outermost layer of the laminated body including a plurality of connecting terminal portions disposed in a mounting area for a semiconductor chip so as to flip-chip mount the semiconductor chip, a solder resist layer being disposed as the insulating layer in an outermost layer of the laminated body,…

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What does patent US9516751B2 cover?
To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10 . The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting …
Who is the assignee on this patent?
Ngk Spark Plug Co
What technology area does this patent fall under?
Primary CPC classification H05K3/3452. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).