Apparatus for gain selection with compensation for parasitic elements and associated methods

Patent metadata

Field	Value
Publication number	US-9515671-B1
Application number	US-201514732701-A
Country	US
Kind code	B1
Filing date	Jun 6, 2015
Priority date	Jun 6, 2015
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

First claim

The invention claimed is:

1. An apparatus comprising:
a first circuit having a first programmable gain, the first circuit including a first set of components having parasitic elements; and
a second circuit having a second programmable gain, the second circuit including a second set of components having parasitic elements,
wherein the apparatus has a gain that is a product of the first and second programmable gains, and wherein a gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

2. The apparatus according to claim 1 , wherein the first circuit comprises a circuit for programming a reference voltage.

3. The apparatus according to claim 1 , wherein the second circuit comprises a circuit for programming a gain of an output stage of the apparatus.

4. The apparatus according to claim 1 , wherein the first set of components comprises a first switch having a parasitic resistance, and the second set of components comprises a second switch having a parasitic resistance M times larger than the parasitic resistance of the first switch, wherein M comprises a positive integer.

5. The apparatus according to claim 4 , wherein the first set of components comprises a first resistor having a first resistance and a second resistor having a second resistance, and wherein the second set of components comprises a third resistor having a third resistance and a fourth resistor having a fourth resistance, wherein the third resistance is M times larger than the first resistance and the fourth resistance is M times larger than the second resistance.

6. The apparatus according to claim 1 , wherein the first circuit receives as an input a reference voltage and produces as an output a scaled version of the reference voltage.

7. The apparatus according to claim 6 , wherein the apparatus has an output signal, and wherein the second circuit receives the output signal of the apparatus as an input, and produces a scaled version of the output signal of the apparatus as an output.

8. The apparatus according to claim 1 , wherein the first circuit comprises a first scaling circuit coupled to a buffer.

9. The apparatus according to claim 8 , wherein the second circuit comprises a second scaling circuit coupled to an output stage.

10. An apparatus comprising:
a digital-to-analog converter (DAC) to convert a digital input signal to an analog output signal, the DAC comprising:
a first circuit to accept a voltage and to provide a scaled version of the voltage as a reference voltage based on a first programmable gain;
a resistor DAC (RDAC) coupled to receive the reference voltage and to generate first and second voltages based on a digital input of the DAC; and
a second circuit coupled to receive the first and second voltages and to provide the analog output signal based on a digital input of the DAC and based on a second programmable gain,
wherein the DAC has a gain that is a product of the first and second programmable gains, and wherein a gain error of the DAC is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

11. The apparatus according to claim 10 , wherein the first circuit comprises a first set of components having parasitic elements, and wherein the second circuit comprises a second set of components having parasitic elements.

12. The apparatus according to claim 11 , wherein the first set of components comprises a first switch having a parasitic resistance, and the second set of components comprises a second switch having a parasitic resistance M times larger than the parasitic resistance of the first switch, wherein M comprises a positive integer.

13. The apparatus according to claim 11 , wherein the first set of components comprises a first resistor having a first resistance and a second resistor having a second resistance, and wherein the second set of components comprises a third resistor having a third resistance and a fourth resistor having a fourth resistance, wherein the third resistance is M times larger than the first resistance and the fourth resistance is M times larger than the second resistance, wherein M comprises a positive integer.

14. The apparatus according to claim 10 , wherein the first circuit comprises a first scaling circuit coupled to a buffer, and wherein the second circuit comprises an interpolator coupled to an output stage, and a second scaling circuit coupled to the output stage.

15. A method of canceling a gain error in an electronic apparatus that has a gain that is a product of first and second programmable gains, the method comprising:
receiving a voltage and scaling the voltage using a first circuit having the first programmable gain and includes a first set of components having parasitic elements to generate a first scaled voltage; and
receiving an output voltage of the apparatus and scaling the output voltage of the apparatus using a second circuit having the second programmable gain and includes a second set of components having parasitic elements to generate a second scaled voltage,
wherein the gain error resulting from the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

16. The method according to claim 15 , wherein receiving the voltage and scaling the voltage comprises programming a reference voltage of the apparatus, and wherein the second circuit comprises a circuit for programming a gain of an output stage of the apparatus.

17. The method according to claim 15 , wherein the first set of components comprises a first switch having a parasitic resistance, and the second set of components comprises a second switch having a parasitic resistance M times larger than the parasitic resistance of the first switch, wherein M comprises a positive integer.

18. The method according to claim 15 , wherein the first set of components comprises a first resistor having a first resistance and a second resistor having a second resistance, and wherein the second set of components comprises a third resistor having a third resistance and a fourth resistor having a fourth resistance, wherein the third resistance is M times larger than the first resistance and the fourth resistance is M times larger than the second resistance.

19. The method according to claim 15 , further comprising buffering the first scaled voltage.

20. The method according to claim 15 , further comprising using the second scaled voltage as a feedback signal in the second circuit.

Assignees

• Silicon Lab Inc

Inventors

• Thomsen Axel
• Westwick Alan L
• Setiawan Ricky
• Ying Rex Wong Tak

Classifications

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03K5/003

  Changing the DC level (reinsertion of DC component of a television signal H04N5/16) · CPC title

• H03M1/664

  Non-linear conversion not otherwise provided for in subgroups of H03M1/66 · CPC title