Semiconductor devices having isolation insulating layers and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9515172-B2
Application number	US-201514600689-A
Country	US
Kind code	B2
Filing date	Jan 20, 2015
Priority date	Jan 28, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a fin region vertically protruding from an upper surface of the substrate and extending longitudinally in a first direction, the fin region comprising first and second fin subregions spaced apart from each other in the first direction;
a discrete isolation insulating island disposed between the first and second fin subregions, a lower surface of the discrete isolation insulating island contacting a portion of the fin region and the discrete isolation insulating island comprising opposing sidewalls that are parallel to the first direction and exposed by the fin region;
a first gate intersecting the first fin subregion and extending in a second direction different from said first direction;
a second gate intersecting the second fin subregion and extending in the second direction; and
a third gate intersecting the discrete isolation insulating island, extending in the second direction and covering the opposing sidewalls of the discrete isolation insulating island,
wherein each of the first, second and third gates comprises a gate dielectric layer and a gate electrode, and
wherein the gate dielectric layer of the third gate is between the gate electrode of the third gate and the discrete isolation insulating island.

2. The semiconductor device of claim 1 , further comprising:
a first isolation insulating layer extending in the first direction and disposed adjacent to and in contact with sidewalls of the first and second fin subregions, wherein a top surface of the discrete isolation insulating island is higher than a top surface of the first isolation insulating layer.

3. The semiconductor device of claim 2 ,
wherein the third gate intersects the first isolation insulating layer, and
wherein a bottom surface of the third gate disposed on the first isolation insulating layer is lower than the top surface of the discrete isolation insulating island.

4. The semiconductor device of claim 1 , wherein the fin region comprises a third fin subregion underneath the discrete isolation insulating island, and
wherein an upper surface of the third fin subregion is between an uppermost surface of the fin region and the upper surface of the substrate.

5. A semiconductor device comprising:
a fin region vertically protruding from an upper surface of a substrate and extending in a first direction that is parallel to the upper surface of the substrate, wherein the fin region comprises first and second fin subregions that are spaced apart from each other in the first direction, and a lower portion of the fin region comprises opposing sidewalls that are parallel to the first direction;
a first isolation insulating layer and a second isolation insulating layer on the respective opposing sidewalls of the lower portion of the fin region, entireties of uppermost surfaces of the first and second isolation insulating layers being lower than an uppermost surface of the fin region;
a discrete isolation insulating island between the first and second fin subregions;
a first gate and a second gate crossing over the fin region and extending in a second direction that is parallel to the upper surface of the substrate and is different from the first direction, the first gate and the second gate extending on the uppermost surfaces of the first and second isolation insulating layers; and
a third gate crossing over the fin region and disposed between the first and second gates, the third gate overlapping the discrete isolation insulating island in plan view and the third gate extending on the uppermost surfaces of the first and second isolation insulating layers.

6. The semiconductor device of claim 5 , wherein the discrete isolation insulating island comprises opposing sidewalls that are parallel to the first direction and exposed by the fin region,
wherein the uppermost surfaces of the first and second isolation insulating layers are lower than an uppermost surface of the discrete isolation insulating island, and the first and second isolation insulating layers expose the opposing sidewalls of the discrete isolation insulating island, and
wherein the third gate extends on the opposing sidewalls and the uppermost surface of the discrete isolation insulating island.

7. The semiconductor device of claim 5 , wherein the discrete isolation insulating island comprises opposing sidewalls that are parallel to the first direction and exposed by the fin region, and
wherein the first isolation insulating layer and the second isolation insulating layer contact the respective opposing sidewalls of the discrete isolation insulating island.

8. The semiconductor device of claim 5 , wherein the uppermost surface of the first isolation insulating layer is lower than an uppermost surface of the discrete isolation insulating island.

9. The semiconductor device of claim 5 further comprising:
a source/drain region in the fin region adjacent a side of the first gate, the source/drain region having a first conductivity type; and
a punch-through stop layer in the fin region under the discrete isolation insulating island, the punch-through stop layer having a second conductivity type that is different from the first conductivity type.

10. The semiconductor device of claim 5 , wherein the third gate comprises a gate dielectric layer and a gate electrode, and the gate dielectric layer is between the gate electrode and the discrete isolation insulating island.

11. The semiconductor device of claim 5 , wherein an uppermost surface of the discrete isolation insulating island is coplanar with the uppermost surface of the fin region.

12. The semiconductor device of claim 5 , wherein the discrete isolation insulating island comprises opposing sidewalls that are parallel to the first direction and exposed by the fin region, and
wherein the opposing sidewalls of the lower portion of the fin region are coplanar with the respective opposing sidewalls of the discrete isolation insulating island.

13. The semiconductor device of claim 9 , wherein the discrete isolation insulating island contacts the punch-through stop layer.

14. The semiconductor device of claim 1 , wherein an uppermost surface of the discrete isolation insulating island is coplanar with an uppermost surface of the fin region.

15. A semiconductor device comprising:
a substrate;
a fin region vertically protruding from an upper surface of the substrate and extending longitudinally in a first direction, the fin region comprising first and second fin subregions that are spaced apart from each other in the first direction and a recess between the first and second fin subregions;
a first isolation insulating layer disposed in the recess, a lower surface of the first isolation insulating layer contacting a portion of the fin region that defines a lower surface of the recess and the first isolation insulating layer comprising opposing sidewalls that are parallel to the first direction and are exposed by the fin region;
a first gate intersecting the first fin subregion and extending in a second direction different from the first direction;
a second gate intersecting the second fin subregion and extending in the second direction; and
a third gate intersecting the first isolation insulating layer, extending in the second direction and covering the opposing sidewalls of the first isolation insulating layer,
wherein the first, second and third gates comprise respective gate dielectric layers and respective gate electrodes, and
wherein the gate dielectric layer of the third gate is between the gate electrode of the third gate and the f

Assignees

• Shin Heonjong
• Kim Sungmin
• Kim Byungseo
• Paak Sunhom Steve
• Bae Hyunjun
• Samsung Electronics Co Ltd

Inventors

• Shin Heonjong
• Kim Sungmin
• Kim Byungseo
• Paak Sunhom Steve
• Bae Hyunjun

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W10/012 Primary

  using local oxidation of silicon [LOCOS] · CPC title

• H10D84/834

  comprising FinFETs · CPC title