Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9515170-B2
Application number	US-201615017459-A
Country	US
Kind code	B2
Filing date	Feb 5, 2016
Priority date	Oct 22, 2007
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on other side thereof, and a gate electrode formed between said source region and said drain region to surround said fin-shaped semiconductor portion with a gate insulating film interposed therebetween, the method for manufacturing a semiconductor device comprising the steps of:
forming an insulating film on a semiconductor layer and further forming a film of polysilicon;
implanting a silicon ion into said polysilicon to amorphize said polysilicon;
patterning said polysilicon amorphized in a predetermined shape;
forming a sidewall on a side face of said polysilicon patterned; and
sequentially etching said insulating film and said semiconductor layer, using as a mask said sidewall from which said polysilicon is removed, to form said fin-shaped semiconductor portion.

2. A method for manufacturing a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on other side thereof, and a gate electrode foimed between said source region and said drain region to surround said fin-shaped semiconductor portion with a gate insulating film interposed therebetween, the method for manufacturing a semiconductor device comprising the steps of:
sequentially laminating polysilicon, an insulating film and a carbon hard mask on said fin-shaped semiconductor portion with said gate insulating film interposed therebetween;
implanting an inactive ion into said carbon hard mask under a condition that said inactive ion does not reach said insulating film below said carbon hard mask;
patterning said carbon hard mask into which said inactive ion has been implanted in a predetermined shape with a resist;
and sequentially etching said insulating film and said polysilicon by using said carbon hard mask patterned to form said gate electrode.

3. The method for manufacturing a semiconductor device according to claim 2 , wherein said inactive ion is an ion of any one of Ar, He, Ne, F, N, Xe and Kr.

4. A method for manufacturing a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on other side thereof, and a gate electrode formed between said source region and said drain region to surround said fin-shaped semiconductor portion with a gate insulating film interposed therebetween, the method for manufacturing a semiconductor device comprising the step of, with control of an implanting condition so that a range of an impurity is a vicinity of an interface of said fin-shaped semiconductor portion with an oxide film formed on said fin-shaped semiconductor portion, implanting an impurity to form a diffusion layer.

Assignees

• Renesas Electronics Corp

Inventors

• Iwamatsu Toshiaki
• Terada Takashi
• Shinohara Hirofumi
• Ishikawa Kozo
• Tsuchiya Ryuta
• Hayashi Kiyoshi

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P30/208

  of electrically inactive species · CPC title