Selective atomic layer deposition process utilizing patterned self assembled monolayers for 3D structure semiconductor applications

Patent metadata

Field	Value
Publication number	US-9515166-B2
Application number	US-201414276780-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	Apr 10, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

First claim

The invention claimed is:

1. A method of forming a structure with desired materials on a substrate comprising:
depositing a self-assembled monolayer on a structure disposed on a substrate;
performing a directional plasma process on the self-assembled monolayer to pattern the self-assembled monolayer;
forming a patterned self-assembled monolayer on a circumference of the structure formed on the substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among the self-assembled monolayer; and
performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

2. The method of claim 1 , wherein the directional plasma process further comprises:
doping ions predominantly into the self-assembled monolayer disposed on a first sidewall of the structure to form the treated layer.

3. The method of claim 2 , wherein doping ions further comprises:
leaving the self-assembled monolayer formed on a second sidewall of the structure without ions doped thereto.

4. The method of claim 2 , wherein doping ions further comprises:
doping the ions into the self-assembled monolayer formed on the first sidewall of the substructure with an ion incident angle of between about 0 degrees and 60 degrees.

5. The method of claim 1 , wherein the directional plasma process further comprises:
doping ions predominantly into the first sidewall of the structure to form the treated layer.

6. The method of claim 1 , further comprising:
forming the self-assembled monolayer on the second sidewall of the substrate where the treated layer is absent.

7. The method of claim 1 , wherein depositing the self-assembled monolayer further comprises:
providing the substrate in a liquid based solution or a gas phase vapor with precursors to form the self-assembled monolayer.

8. The method of claim 1 , wherein performing the atomic layer deposition process further comprises:
pulsing a first reactant gas to provide a first type of atoms to form a first monolayer of the material layer predominantly and selectively on the self-assembled monolayer.

9. The method of claim 8 , further comprising:
pulsing a second reactant gas to provide a second type of atoms to form a second monolayer of the material layer predominantly and selectively on the first monolayer of the material layer.

10. The method of claim 1 , wherein the structure is a fin structure used in three-dimensional stacking of fin field effect transistor (FinFET) for semiconductor chips.

11. A method of forming a fin structure with different materials on different sidewalls on a substrate comprising:
performing a directional plasma process to form a patterned self-assembled layer including a treated layer formed on a first sidewall of a structure and a self-assembled layer formed on a second sidewall of the structure formed on the substrate; and
selectively depositing a material layer predominantly on the self-assembled layer.

12. The method of claim 11 , wherein selectively depositing the material layer further comprises:
performing an atomic layer deposition process to form the material layer predominantly on the self-assembled layer.

13. The method of claim 11 , wherein performing the directional plasma process further comprising:
performing the directional plasma process to predominantly dope ions into the first sidewall of the structure, forming the treated layer predominantly on the first sidewall of the structure; and
depositing the self-assembled layer predominantly on the second sidewall of the structure where the treated layer is absent.

14. The method of claim 13 , wherein performing the directional plasma process further includes:
doping the ions into the first sidewall of the substructure with an ion incident angle of between about 0 degrees and 60 degrees.

15. The method of claim 11 , performing the directional plasma process further comprising:
depositing the self-assembled layer on the circumference of the structure;
performing the directional plasma process to predominantly dope ions into the first sidewall of the structure, forming the treated layer predominantly on the first sidewall of the structure.

16. The method of claim 15 , further comprising:
leaving the self-assembled layer formed on the second sidewall of the structure substantially unchanged without ion doping.

17. The method of claim 11 , the structure is a fin structure used in three-dimensional stacking of fin field effect transistor (FinFET) for semiconductor chips.

18. A method for forming a fin structure with different materials formed on different locations of the fin structure comprising:
performing an atomic layer deposition process to form a material layer on a substrate having a patterned self-assembled layer formed on a fin structure, wherein material layer is selectively formed a designated location of the fin structure where the patterned self-assembly defines to grow.

19. The method of claim 18 , wherein the designated location is a first sidewall of the fin structure used in three-dimensional stacking of fin field effect transistor (FinFET) for semiconductor chips.

Assignees

• Applied Materials Inc

Inventors

• Nemani Srinivas D
• Yieh Ellie Y
• Godet Ludovic
• Fan Yin

Classifications

• H10P30/40

  into insulating materials · CPC title

• H10P14/6532

  by exposure to a plasma · CPC title

• H10P14/6518

  by introduction of substances into an already-existing insulating layer · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6506 Primary

  Formation of intermediate materials · CPC title