Vertical MOSFET device with steady on-resistance

Patent metadata

Field	Value
Publication number	US-9515145-B2
Application number	US-201414768542-A
Country	US
Kind code	B2
Filing date	Feb 14, 2014
Priority date	Feb 28, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a drift layer of a first conductivity type formed on a front surface of said semiconductor substrate;
a first well region of a second conductivity type formed on a front surface side of said drift layer;
a second well region of the second conductivity type formed on the front surface side of said drift layer;
first and second source regions of the first conductivity type formed in respective of said first and said second well regions on the front surface side of said drift layer;
a first electrode formed on a front surface of said drift layer, said first electrode being in contact with said first and second source regions;
a second electrode formed on a back surface of said semiconductor substrate; and
a gate structure forming a channel in said first well region and a channel in said second well region,
wherein a channel resistance value of the channel formed in said first well region has a temperature characteristic that the channel resistance value decreases with increasing temperature and a channel resistance value of the channel formed in said second well region has a temperature characteristic that the channel resistance value increases with increasing temperature.

2. The semiconductor device according to claim 1 , wherein said first well region and said second well region are formed in a same cell.

3. The semiconductor device according to claim 1 , wherein an impurity concentration of the second conductivity type in said first well region is higher than an impurity concentration of the second conductivity type in said second well region.

4. The semiconductor device according to claim 3 , wherein
said first conductivity type is n type,
said second conductivity type is p type,
said gate structure includes:
a gate oxide film formed to be in contact with said drift layer and said first well region or said second well region; and
a gate metal formed on said gate oxide film,

both an interface state density at an interface between said first well region and said gate oxide film and an interface state density at an interface between said second well region and said gate oxide film are less than or equal to 1×10 12 eV −1 cm −2 ,
a depleted region in which a conductivity is inverted in the formation of said channel of said first well region has an effective acceptor density of 3.5×10 12 eV −1 cm −2 or more, and
a depleted region in which a conductivity is inverted in the formation of said channel of said second well region has an effective acceptor density of less than 3.5×10 12 eV −1 cm −2 .

5. The semiconductor device according to claim 3 , wherein
said first conductivity type is n type,
said second conductivity type is p type,
said gate structure includes:
a gate oxide film formed to be in contact with said drift layer and said first well region or said second well region; and
a gate metal formed on said gate oxide film,

both an interface state density at an interface between said first well region and said gate oxide film and an interface state density at an interface between said second well region and said gate oxide film are less than or equal to 1×10 12 eV −1 cm −2 ,
a depleted region in which a conductivity is inverted in the formation of said channel of said first well region has an effective acceptor concentration of 1.0×10 17 eV −1 cm −3 or more, and
a depleted region in which a conductivity is inverted in the formation of said channel of said second well region has an effective acceptor concentration of less than 1.0×10 17 cm −3 .

6. The semiconductor device according to claim 1 , wherein
said gate structure includes:
a gate oxide film formed to be in contact with said drift layer and said first well region or said second well region; and
a gate metal formed on said gate oxide film, and

an interface state density at an interface between said gate oxide film and said first well region is greater than an interface state density at an interface between said gate oxide film and said second well region.

7. The semiconductor device according to claim 6 , wherein
the interface state density at the interface between said first well region and said gate oxide film is more than or equal to 1×10 12 eV −1 cm −2 , and
the interface state density at the interface between said second well region and said gate oxide film is less than 1×10 12 eV −1 cm −2 .

8. The semiconductor device according to claim 1 , comprising a plurality of said first well regions and a plurality of said second well regions,
wherein said plurality of first well regions and said plurality of second well regions are arranged alternately in accordance with a constituent ratio between said plurality of first well regions and said plurality of second well regions.

9. The semiconductor device according to claim 8 , wherein the constituent ratio between said plurality of first well regions and said plurality of second well regions is adjusted such that a resistance value between said first electrode and said second electrode is constant while a current flows between said first electrode and said second electrode.

10. The semiconductor device according to claim 1 , wherein said semiconductor substrate is a silicon carbide substrate.

11. The semiconductor device according to claim 1 , wherein said semiconductor substrate has the first conductivity type.

12. The semiconductor device according to claim 1 , comprising a third well region of the second conductivity type formed in the front surface of said drift layer, wherein
said gate structure forms a channel in said third well region, and
a channel resistance value of the channel formed in said third well region has a temperature characteristic that the channel resistance value increases with increasing temperature or a temperature characteristic that the channel resistance value decreases with increasing temperature.

13. A semiconductor device comprising:
a semiconductor substrate;
a drift layer of a first conductivity type formed on a front surface of said semiconductor substrate;
a first well region of a second conductivity type formed on a front surface side of said drift layer;
a second well region of the second conductivity type formed on the front surface side of said drift layer;
first and second source regions of the first conductivity type formed in respective of said first well region and said second well region on the front surface side of said drift layer;
a first electrode formed on a front surface of said drift layer, said first electrode being in contact with said first and second source regions;
a second electrode formed on a back surface of said semiconductor substrate; and
a gate structure forming a channel in said first well region and a channel in said second well region, wherein
a resistance value of a current path formed between said first electrode and said second electrode with the channel of said first well region located therebetween has a temperature characteristic that the resistance value decreases with increasing temperature, and
a resistance value of a current path formed between said first electrode and said second electrode with the channel of said second well region located therebetween has a temperature characteristic that the resistance value increases with increasing temperature.

14. The semiconductor device according to claim 13 , wherein said first well region and said second well region are formed in a same cell.

15. The semiconductor device according to claim 13 , wherein an impurity concentratio

Assignees

• Mitsubishi Electric Corp

Inventors

• Furuhashi Masayuki
• Okabe Hiroaki
• Watanabe Tomokatsu
• Imaizumi Masayuki

Classifications

• H10D64/01366 Primary

  the semiconductor being silicon carbide · CPC title

• H10D12/032

  of vertical IGBTs · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title