Methods and apparatus for solder connections

Patent metadata

Field	Value
Publication number	US-9515036-B2
Application number	US-201213452507-A
Country	US
Kind code	B2
Filing date	Apr 20, 2012
Priority date	Apr 20, 2012
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.

First claim

What is claimed is:

1. An apparatus, comprising:
a substrate having a first conductive feature and a second conductive feature on a surface, each of the first conductive feature and the second conductive feature including a conductive terminal;
at least one first stud bump bonded to the first conductive feature and extending in a direction normal to the surface of the substrate;
at least one second stud bump bonded to the second conductive feature and extending in a direction normal to the surface of the substrate, the first conductive feature and the second conductive feature having a different number of distinct and separated stud bumps; and
a solder connection formed on each of the first conductive feature and the second conductive feature enclosing the at least one first stud bump and the at least one second stud bump.

2. The apparatus of claim 1 , wherein the at least one first stud bump comprises one selected from the group consisting essentially of copper and gold.

3. The apparatus of claim 1 , wherein the first conductive feature further comprises an under bump metallization layer overlying an opening in a passivation layer and beneath the at least one first stud bump.

4. The apparatus of claim 3 , wherein the first conductive feature further comprises a finish layer overlying the under bump metallization layer and beneath the at least one first stud bump.

5. The apparatus of claim 1 , wherein the first conductive feature comprises a finish layer overlying the conductive terminal and beneath the at least one first stud bump, wherein the at least one first stud bump is bonded directly to the finish layer.

6. The apparatus of claim 5 , wherein the finish layer comprises one selected from the group consisting essentially of gold, nickel, palladium, electroless nickel-immersion gold and electroless nickel-electroless palladium-immersion gold.

7. The apparatus of claim 1 , wherein the at least one first stud bump further comprises three or more stud bumps.

8. An apparatus, comprising:
a semiconductor substrate having a plurality of integrated circuits formed therein;
a plurality of conductive features formed on a surface of the semiconductor substrate and coupled to circuitry within the semiconductor substrate;
at least one stud bump formed on at least some of the conductive features, the at least one stud bump bonded to the conductive features and extending in a direction normal to the surface of the semiconductor substrate, wherein a first subset of the at least some of the conductive features has a first number of distinct and separated stud bumps and a second subset of the at least some of the conductive features has a second number of distinct and separated stud bumps, the first number being greater than the second number, wherein the second subset of the at least some of the conductive features is closer to a center of the semiconductor substrate in a plan view than the first subset of the at least some of the conductive features; and
a solder connection formed over each of the conductive features and surrounding the at least one stud bump on the at least some of the conductive features.

9. The apparatus of claim 8 , wherein the conductive features comprise an under bump metallization layer formed over a passivation layer and extending into openings in the passivation layer to a conductive terminal.

10. The apparatus of claim 8 , wherein each of the conductive features comprise a finish layer formed over a conductive terminal.

11. The apparatus of claim 8 , wherein the at least one stud bump each comprise one selected from the group consisting essentially of copper and gold.

12. The apparatus of claim 1 , further comprising a third conductive feature, the third conductive feature having no stud bumps bonded thereto.

13. The apparatus of claim 8 , wherein at least one of the plurality of conductive features have no stud bumps bonded thereto.

14. An apparatus comprising:
a substrate having electrical circuitry;
a first conductive feature on the substrate, the first conductive feature being electrically coupled to the electrical circuitry;
a second conductive feature on the substrate;
a first number of first stud bumps on the first conductive feature, the first number being one or more;
an electrical connection formed over the first conductive feature and around the first stud bumps;
a second number of second stud bumps on the second conductive feature, the second number being greater than the first number; and
a third conductive feature on the substrate, wherein the third conductive feature is free from stud bumps.

15. The apparatus of claim 14 , wherein the second conductive feature is further from a center of the apparatus than the first conductive feature in a plan view.

16. The apparatus of claim 14 , wherein the conductive feature comprises a conductive terminal and an under bump metallization, wherein a passivation layer is interposed between a portion of the conductive terminal and the under bump metallization.

17. The apparatus of claim 14 , wherein the third conductive feature is closer to a center of the substrate than the first conductive feature and the second conductive feature.

18. The apparatus of claim 12 , wherein the third conductive feature is closer to a center of the substrate in a plan view than the first conductive feature and the second conductive feature.

19. The apparatus of claim 13 , wherein the at least one of the plurality of conductive features having no stud bumps is closer the center of the semiconductor substrate in a plan view than the second subset of the at least some of the conductive features.

Assignees

• Yu Chen-Hua
• Tsai Hao-Yi
• Lee Chien-Hsiun
• Liu Chung-Shi
• Chen Hsien-Wei
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Tsai Hao-Yi
• Lee Chien-Hsiun
• Liu Chung-Shi
• Chen Hsien-Wei

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/01257

  by reflowing · CPC title