Chromium/titanium/aluminum-based semiconductor device contact fabrication

US9514947B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9514947-B2
Application numberUS-201514747150-A
CountryUS
Kind codeB2
Filing dateJun 23, 2015
Priority dateJun 25, 2007
Publication dateDec 6, 2016
Grant dateDec 6, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: forming an ohmic contact to a group III nitride layer in a semiconductor structure, the group III nitride layer having an Aluminum molar fraction of at least approximately 0.5, wherein the forming includes: forming a multi-layer structure comprising: the semiconductor structure; a Chromium layer over the semiconductor structure; a Titanium layer directly on the Chromium layer; and an Aluminum layer directly on the Titanium layer; and annealing the multi-layer structure. 2. The method of claim 1 , the multi-layer structure further comprising a barrier layer directly on the Aluminum layer. 3. The method of claim 2 , wherein the barrier layer is a Titanium layer. 4. The method of claim 2 , the multi-layer structure further comprising a Gold layer directly on the barrier layer. 5. The method of claim 4 , wherein at least one layer in the multi-layer structure is discontinuous. 6. The method of claim 5 , wherein the at least one layer includes the Chromium layer. 7. The method of claim 1 , the multi-layer structure further comprising: a buffer layer directly on the Aluminum layer; a barrier layer directly on the buffer layer; and a surface protective layer directly on the barrier layer. 8. The method of claim 7 , wherein the barrier layer includes at least one of: Titanium, Chromium, Nickel, Cobalt, Platinum, Lead, Molybdenum, or Tungsten. 9. The method of claim 1 , wherein the annealing is performed at a temperature between approximately 850 degrees Celsius and approximately 1100 degrees Celsius. 10. A method of fabricating a semiconductor device comprising: forming an ohmic contact on a semiconductor structure of the semiconductor device, wherein the forming includes: forming a multi-layer structure comprising: the semiconductor structure; a Chromium layer over the semiconductor structure; a Titanium layer directly on the Chromium layer; and an Aluminum layer directly on the Titanium layer; and annealing the multi-layer structure at a temperature between approximately 850 degrees Celsius and approximately 1100 degrees Celsius. 11. The method of claim 10 , wherein at least one layer in the multi-layer structure is discontinuous. 12. The method of claim 11 , wherein the at least one layer includes the Chromium layer, and wherein the method further comprises depositing a second metal, distinct from the Chromium in a set of openings of the Chromium layer. 13. The method of claim 12 , wherein the second metal has at least one of: improved adhesive properties or improved reflective properties than the Chromium layer. 14. The method of claim 10 , wherein the forming the multi-layer structure further includes forming a Titanium layer directly on the Aluminum layer. 15. The method of claim 10 , wherein the ohmic contact is to a group III nitride layer in the semiconductor structure, and wherein the group III nitride layer has an Aluminum molar fraction of at least approximately 0.5. 16. The method of claim 10 , wherein the device is one of: a light emitting diode, a laser, a field effect transistor, a solar cell, a charge coupled device, a Schottky diode, or a p-n junction diode. 17. A method of fabricating a light emitting device, the method comprising: forming an ohmic contact to a group III nitride layer in a semiconductor structure of the light emitting device, the group III nitride layer having an Aluminum molar fraction of at least approximately 0.5, wherein the forming includes: forming a multi-layer structure comprising: the semiconductor structure; a Chromium layer over the semiconductor structure; a Titanium layer directly on the Chromium layer; and an Aluminum layer directly on the Titanium layer; and annealing the multi-layer structure. 18. The method of claim 17 , wherein the annealing is performed at a temperature between approximately 850 degrees Celsius and approximately 1100 degrees Celsius. 19. The method of claim 17 , wherein at least one layer in the multi-layer structure is discontinuous. 20. The method of claim 19 , wherein the at least one layer includes the Chromium layer.

Assignees

Inventors

Classifications

  • AIIIBV compounds · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

  • Cross-sectional shape, i.e. in side view · CPC title

  • Bond pads having multiple stacked layers · CPC title

  • of bond pads · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9514947B2 cover?
A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior ar…
Who is the assignee on this patent?
Sensor Electronic Tech Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/40. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).