Volatile memory self-defresh

Patent metadata

Field	Value
Publication number	US-9514802-B2
Application number	US-201514668927-A
Country	US
Kind code	B2
Filing date	Mar 25, 2015
Priority date	Oct 27, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Embodiments of the inventive concept include a volatile memory device including a memory cell array, the memory cell array including multiple rows and/or banks to store data. The memory device can include an address decoder coupled to the memory cell array. The memory device can include a control logic section coupled to the address decoder. The control logic section can include a defresh logic section configured to intentionally violate, by an activate command, a row precharge time (T RP ) and/or a row active time (T RAS ) for each of the plurality of rows to clean the data from the memory cell array. Memory data can be cleaned from the memory cell array responsive to the violations.

First claim

What is claimed is:

1. A volatile memory device, comprising:
a memory cell array including a plurality of rows configured to store data;
an address decoder coupled to the memory cell array; and
a control logic section coupled to the address decoder, the control logic section including a defresh logic section configured to violate, by an activate command, a row precharge time (T RP ) for each of the plurality of rows to clean the data from the memory cell array.

2. The volatile memory device of claim 1 , wherein the defresh logic section is configured to violate the T RP for each of the plurality of rows responsive to a memory reset.

3. The volatile memory device of claim 1 , wherein the defresh logic section is configured to violate the T RP for each of the plurality of rows responsive to a memory power-on.

4. The volatile memory device of claim 1 , further comprising delay logic, wherein the address decoder is configured to update a row address associated with one of the plurality of rows after a delay caused by the delay logic.

5. The volatile memory device of claim 1 , wherein the defresh logic section includes a defresh counter that is configured to begin counting a time T at substantially a start time of the T RP and end counting the time T before an end time of the T RP .

6. The volatile memory device of claim 5 , wherein the address decoder is configured to update a row address associated with one of the plurality of rows responsive to an expiration of the time T.

7. The volatile memory device of claim 6 , wherein the control logic section is configured to cause the activate command to violate the T RP after the row address is updated and responsive to the expiration of the time T.

8. The volatile memory device of claim 7 , wherein the time T is less than the T RP .

9. A computer-implemented method for defreshing a volatile memory, the method comprising:
storing data in a plurality of rows of a memory cell array of the volatile memory;
detecting at least one of a memory power-on or a memory reset of the volatile memory;
initiating a reset procedure responsive to the detecting;
initializing the volatile memory responsive to the reset procedure, wherein initializing includes defreshing, by a defresh logic section, the plurality of rows of the memory cell array of the volatile memory, wherein defreshing includes:
violating, by an activate command, a row precharge time (T RP ) for each of the plurality of rows; and
cleaning the data from the plurality of rows of the memory cell array responsive to the violations.

10. The computer-implemented method of claim 9 , further comprising:
violating, by the defresh logic section, the T RP for each of the plurality of rows responsive to the memory reset.

11. The computer-implemented method of claim 9 , further comprising:
violating, by the defresh logic section, the T RP for each of the plurality of rows responsive to the memory power-on.

12. The computer-implemented method of claim 9 , further comprising:
beginning counting, by a defresh counter of the defresh logic section, a time T at substantially a start time of the T RP ; and
ending counting, by the defresh counter, the time T before an end time of the T RP .

13. The computer-implemented method of claim 12 , wherein the time T is less than the T RP .

14. The computer-implemented method of claim 12 , further comprising:
updating, by an address decoder, a row address associated with one of the plurality of rows responsive to an expiration of the time T.

15. The computer-implemented method of claim 14 , further comprising:
causing, by the defresh logic section, the activate command to violate the T RP after updating the row address and responsive to the expiration of the time T.

16. A computer-implemented method for defreshing a volatile memory, the method comprising:
storing data in a plurality of rows of a memory cell array of the volatile memory;
detecting at least one of a memory power-on or a memory reset of the volatile memory;
initiating a reset procedure responsive to the detecting;
initializing the volatile memory responsive to the reset procedure, wherein initializing includes defreshing, by a defresh logic section, the plurality of rows of the memory cell array of the volatile memory, wherein defreshing includes:
activating a first row from among the plurality of rows;
beginning a first row active time (T RAS ) at substantially a same time as activating the first row;
activating a second row from among the plurality of rows before an end time of the first T RAS and before a precharge is initiated for the first row;
violating, by the second row activation, the first T RAS ;
activating a third row from among the plurality of rows before an end time of a second T RAS and before a precharge is initiated for the second row;
violating, by the third row activation, the second T RAS ;
cleaning the data from the plurality of rows of the memory cell array responsive to the violations.

17. The computer-implemented method of claim 16 , further comprising:
violating, by the defresh logic section, the T RAS for each of the plurality of rows responsive to the memory reset.

18. The computer-implemented method of claim 16 , further comprising:
violating, by the defresh logic section, the T RAS for each of the plurality of rows responsive to the memory power-on.

19. The computer-implemented method of claim 16 , further comprising:
updating, by an address decoder, a row address, after activating the first row; and
updating, by the address decoder, the row address, after activating the second row.

20. The computer-implemented method of claim 19 , further comprising:
causing, by the defresh logic section, the activation of the second and third rows to violate the first T RAS and the second T RAS , respectfully.

Assignees

• Guz Zvi
• Yin Liang
• Samsung Electronics Co Ltd

Inventors

• Guz Zvi
• Yin Liang

Classifications

• G11C11/4078 Primary

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title