Test interface board and test system including the same

Patent metadata

Field	Value
Publication number	US-9513333-B2
Application number	US-201414458241-A
Country	US
Kind code	B2
Filing date	Aug 12, 2014
Priority date	Sep 12, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A test interface board includes a substrate including a power plane electrically connected to at least one power terminal of a semiconductor device under test, and a ground plane electrically connected to at least one ground terminal of the semiconductor device under test, and a voltage regulator arranged on the substrate and configured to supply, via the power plane and the ground plane, to the semiconductor device under test, a driving voltage.

First claim

What is claimed is:

1. A test interface board, comprising:
a substrate including a power plane electrically connected to at least one power terminal of a semiconductor device under test, and a ground plane electrically connected to at least one ground terminal of the semiconductor device under test; and
a voltage regulator arranged on the substrate and configured to supply, via the power plane and the ground plane, to the semiconductor device under test, a driving voltage,
wherein the voltage regulator is electrically connected to a power supply, and the voltage regulator comprises:
an input terminal to which a power voltage of the power supply is applied;
a ground terminal electrically connected to a ground of the power supply and to the ground plane; and
an output terminal electrically connected to the power plane,
wherein the voltage regulator further comprises a reference voltage generation unit configured to generate a reference voltage, and
wherein the output terminal is configured to supply, via the power plane, to the semiconductor device under test, the driving voltage based at least on the reference voltage.

2. The test interface board of claim 1 , wherein:
the voltage regulator further comprises a reference voltage input terminal to which a reference voltage is applied, and
the output terminal of the voltage regulator is configured to supply, via the power plane, to the semiconductor device under test, the driving voltage based at least on the reference voltage.

3. The test interface board of claim 2 , wherein the voltage regulator further comprises:
a comparison unit configured to compare the reference voltage and the driving voltage, and to output a control signal; and
an output unit configured to supply the driving voltage and an associated current to the power plane based at least on the control signal, wherein the driving voltage is based at least on the power voltage from the power supply.

4. The test interface board of claim 3 , wherein:
when the driving voltage has a level that is higher than a level of the reference voltage, the voltage regulator is configured to decrease an amount of the current supplied to the power plane to decrease the level of the driving voltage, and
when the driving voltage has a level that is lower than the level of the reference voltage, the voltage regulator is configured to increase the amount of the current supplied to the power plane to increase the level of the driving voltage.

5. The test interface board of claim 1 , wherein:
the reference voltage generation unit comprises a diode connected between the input terminal and the ground terminal, or between the output terminal and the ground terminal, and
the reference voltage corresponds to a breakdown voltage.

6. The test interface board of claim 1 , wherein the voltage regulator further comprises:
a comparison voltage generation unit configured to generate a comparison voltage based at least on the driving voltage;
a comparison unit configured to compare the reference voltage and the comparison voltage, and to output a control signal; and
an output unit configured to supply the driving voltage and an associated current to the power plane based at least on the control signal, wherein the driving voltage is based at least on the power voltage from the power supply.

7. The test interface board of claim 6 , wherein:
the comparison voltage generation unit comprises a variable device,
a ratio of the comparison voltage to the driving voltage is determined by the variable device, and
the driving voltage is determined by a value obtained by dividing the reference voltage by the ratio.

8. The test interface board of claim 1 , wherein:
the substrate further comprises a plurality of data conductors electrically connected to a plurality of data input/output terminals of the semiconductor device under test, and
the plurality of data conductors are connected to a plurality of data input/output channels of an automatic test equipment apparatus.

9. The test interface board of claim 8 , wherein:
the automatic test equipment apparatus comprises the power supply, and
the automatic test equipment apparatus is configured to output, via a power output channel, the power voltage of the power supply.

10. The test interface board of claim 1 , wherein:
the substrate comprises at least one of another power plane electrically connected to at least one of another power terminal of at least one of another semiconductor device under test,
the substrate comprises at least one of another ground plane electrically connected to at least one of another ground terminal of the at least one of another semiconductor device under test, and
the test interface board further comprises at least one of another voltage regulator arranged on the substrate and configured to supply, via the at least one of another power plane and the at least one of another ground plane, to the at least one of another semiconductor device under test, the driving voltage.

11. The test interface board of claim 1 , wherein:
the power plane is further electrically connected to the at least one power terminal of at least one of another semiconductor device under test,
the ground plane is further electrically connected to the at least one ground terminal of the at least one of another semiconductor device under test, and
the voltage regulator is configured to supply, via the power plane and the ground plane, to the at least one of another semiconductor device under test, the driving voltage.

12. The test interface board of claim 1 , wherein the substrate further comprises:
at least one power contact electrically connecting the power plane to the at least one power terminal of the semiconductor device under test; and
at least one ground contact electrically connecting the ground plane to the at least one ground terminal of the semiconductor device under test.

13. The test interface board of claim 12 , wherein:
the substrate further comprises a first decoupling capacitor connected between the at least one power contact and the at least one ground contact, and
the first decoupling capacitor has a capacitance that is greater than 1 pF and less than 1000 pF.

14. The test interface board of claim 1 , wherein:
the substrate further comprises a second decoupling capacitor connected between the power plane and the ground plane, and
the second decoupling capacitor has a capacitance that is greater than 1 μF and less than 1000 μF.

15. The test interface board of claim 1 , wherein:
the semiconductor device under test is a semiconductor die formed by splitting a semiconductor wafer through a dicing process, and comprises a semiconductor circuit, and
the test interface board is a probe card comprising needles directly connected to terminals of the semiconductor die.

16. The test interface board of claim 1 , wherein:
the semiconductor device under test is a semiconductor package in which a semiconductor circuit is formed, and
the test interface board is a hi-fix board on which at least one socket for loading at least one semiconductor package is mounted.

17. A test interface board for testing a semiconductor device under test, the semiconductor device under test comprising a plurality of power terminals and a plurality of ground terminals, the test interface board comprising:
a substrate comprising a first power plane electrically connected to a first power terminal from among the plurality of power terminals of the semiconductor device under test, a second power plane electrically connected to

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Ki-Jae
• Yoo Jong-Woon

Classifications

• G01R31/3004 Primary

  Current or voltage test · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C2029/5602

  Interface to device under test · CPC title

• G11C29/56

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G01R31/2839

  using signal generators, power supplies or circuit analysers (G01R31/2879 takes precedence; multimeters G01R15/12, network analysers G01R27/28) · CPC title