Probe card partition scheme

Patent metadata

Field	Value
Publication number	US-9513332-B2
Application number	US-201414459801-A
Country	US
Kind code	B2
Filing date	Aug 14, 2014
Priority date	Oct 14, 2011
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A method of testing an integrated circuit die comprises partitioning a first probe card partition layout of the integrated circuit die having one or more sections comprising a first quantity of section types into a second probe card partition layout having a greater quantity of sections comprising a second quantity of section types, the second quantity of section types being less than the first quantity of section types. The method also comprises using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type included in the second probe card partition layout.

First claim

What is claimed is:

1. A method of testing an integrated circuit die, the method comprising:
partitioning a first probe card partition layout of the integrated circuit die into a second probe card partition layout;
the first probe card partition layout having one or more sections, each section conforming to a member of a first collection of section types, there being a first quantity of members in the first collection;
the second probe card partition layout having a greater quantity of sections than the first probe card partition layout, each section in the second probe card partition layout conforming to a member of a second collection of section types, there being a second quantity of members in the second collection;
the second quantity being less than the first quantity; and

using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type represented in the second probe card partition layout.

2. The method of claim 1 , wherein the second probe card partition layout has a test contact pattern that is symmetric with respect to rotation by a specified angle.

3. The method of claim 1 , further comprising using the same probe card for testing multiple instances of at least one of the one or more different section configurations in the second probe card partition layout.

4. The method of claim 3 , wherein the same probe card is used for testing all instances of the one or more different section configurations of the second probe card partition layout.

5. The method of claim 1 , wherein, for at least one of the one or more section configurations, the second probe card partition layout has a first set of instances of the given configuration interlaced with a second set of instances of the given configuration.

6. The method of claim 5 , further comprising using the same probe card for testing the first and the second set.

7. The method of claim 1 , further comprising adding at least one dummy pad in at least one section configuration of the second probe card partition layout.

8. The method of claim 1 , wherein a number of test contacts of each of the one or more section configurations of the second probe card partition layout is limited within a tester pin count specification.

9. The method of claim 1 , further comprising adding at least one alignment mark to each section configuration of the second probe card partition layout.

10. The method of claim 1 , further comprising using at least one section configuration in the second probe card partition layout for a backside probe card partition layout of the integrated circuit die.

11. The method of claim 1 , wherein each member type in the second collection of section types is a subset of a corresponding member type in the first collection of section types.

12. A probe card partition layout, comprising:
one or more first sections having a first arrangement of pads corresponding to a first angular position of a probe card having a test contact pattern, the first arrangement being arranged on a reference plane and the first angular position being defined relative to an axis of rotation orthogonal to the reference plane;
one or more second sections having a second arrangement of pads corresponding to a second angular position of the probe card, the second orientation also being arranged on the reference plane, the second angular position being rotationally displaced from the first position such that pads of the first arrangement do not overlap pads of the second arrangement; and
at least one alignment mark, a location of each mark being based on a predetermined spatial relationship with a corresponding at least one of (A) at least one of the one or more first sections or (B) at least one the one or more second sections,
wherein the at least one alignment mark is used for tester alignment.

13. The probe card partition layout of claim 12 , wherein the one or more first sections are interlaced with the one or more second sections.

14. The probe card partition layout of claim 12 , wherein at least one dummy pad is added to at least one section of the one or more first sections or the one or more second sections.

15. The probe card partition layout of claim 12 , wherein the probe card is used for testing a backside of the integrated circuit die.

16. The probe card partition layout of claim 12 , wherein a number of test contacts of each section of the probe card partition layout is limited within a tester pin count specification.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Goel Sandeep Kumar
• Wang Mill-Jer

Classifications

• G01R31/2889 Primary

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

• G01R31/31908

  Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns · CPC title

• G01R1/07342

  the body of the probe being at an angle other than perpendicular to test object, e.g. probe card · CPC title

• G01R1/0408

  Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets (G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808) · CPC title