Methods of forming semiconductor structures including MEMS devices and integrated circuits on common sides of substrates, and related structures and devices

Patent metadata

Field	Value
Publication number	US-9511996-B2
Application number	US-201314416860-A
Country	US
Kind code	B2
Filing date	Jul 8, 2013
Priority date	Jul 31, 2012
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit, comprising:
fabricating at least a portion of an integrated circuit on a first major surface of a semiconductor substrate;
depositing a layer of material over the at least a portion of the integrated circuit on a side thereof opposite the first major surface of the semiconductor substrate;
forming at least one transducer cavity recess in an exposed major surface of the layer of material; bonding an SOI-type structure to the exposed major surface of the layer of material the SOI-type structure including a relatively thin layer of material bonded to a relatively thick volume of bulk material with an intermediate material between the relatively thin layer of material and the relatively thick volume of bulk material; removing a portion of the SOI-type structure and leaving the thin layer of material of the SOI-type structure bonded to the layer of material having the at least one transducer cavity recess therein;
configuring a portion of the thin layer of material over the transducer cavity recess to comprise at least a portion of a transducer so as to integrally form at least a portion of a MEMS device over the at least a portion of the integrated circuit on a side thereof opposite the first major surface of the semiconductor substrate; and operatively coupling the MEMS device with the integrated circuit.

2. The method of claim 1 , wherein fabricating the at least a portion of the integrated circuit on the first major surface of the semiconductor substrate comprises forming at least one transistor on the first major surface of the semiconductor substrate.

3. The method of claim 2 , wherein fabricating the at least a portion of the integrated circuit on the first major surface of the semiconductor substrate further comprises forming at least one electrically conductive feature over the first major surface of the semiconductor substrate, the at least one electrically conductive feature electrically coupled with the with an electrically conductive via.

4. The method of claim 1 , further comprising forming a conductive via extending through the layer of material and electrically coupling the MEMS device to the at least a portion of the integrated circuit.

5. The method of claim 4 , further comprising forming another conductive via extending through the semiconductor substrate from the first major surface of the semiconductor substrate to a second major surface of the semiconductor substrate.

6. The method of claim 5 , further comprising operably coupling the MEMS device and the at least a portion of the integrated circuit to a conductive feature of another structure or device by electrically interconnecting the conductive feature of the another structure or device to an end of the another conductive via exposed at the second major surface of the semiconductor substrate.

7. The method of claim 1 , further comprising operably coupling the MEMS device and the at least a portion of the integrated circuit to a conductive feature of another structure or device using a wire bond.

Assignees

• Soitec Silicon On Insulator

Inventors

• Sadaka Mariam
• Aspar Bernard
• Blanchard Chrystelle Lagahe

Classifications

• H03H9/10

  Mounting in enclosures {(constructional combinations of enclosure with electromechanical and other electronic elements H03H9/0538)} · CPC title

• B81C2203/0792

  Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title

• B81C2203/0735

  Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit · CPC title

• B81C1/00238

  Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

• B81B2207/015

  the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title