Manufacturing method of circuit board

Patent metadata

Field	Value
Publication number	US-9510464-B2
Application number	US-201213590815-A
Country	US
Kind code	B2
Filing date	Aug 21, 2012
Priority date	Dec 30, 2009
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A manufacturing method of a circuit board is provided. A circuit substrate having a first surface and at least a first circuit is provided. A dielectric layer having a second surface and covering the first surface and the first circuit is formed on the circuit substrate. The dielectric layer is irradiated by a laser beam to form a first intaglio pattern, a second intaglio pattern and at least a blind via. A first conductive layer is formed in the first intaglio pattern, the second intaglio pattern and the blind via. A barrier layer and a second conductive layer are formed in the second intaglio pattern and the blind via. Parts of the second conductive layer, parts of the barrier layer and parts of the first conductive layer are removed until the second surface of the dielectric layer is exposed, so as to form a patterned circuit structure.

First claim

What is claimed is:

1. A manufacturing method of a circuit board, comprising:
providing a circuit substrate having a first surface and at least a first circuit;
forming a dielectric layer on the circuit substrate, the dielectric layer having a second surface and covering the first surface and the at least a first circuit;
irradiating the dielectric layer by a laser beam to form a first intaglio pattern, a second intaglio pattern, and at least a blind via extending from the second surface of the dielectric layer to the at least a first circuit of the circuit substrate;
forming a first conductive layer in the first intaglio pattern, the second intaglio pattern, and the at least a blind via, wherein the first conductive layer fills the first intaglio pattern and is disposed on an inner wall of the second intaglio pattern and an inner wall of the at least a blind via, and an entire volume of the first intaglio pattern is full of the first conductive layer;
forming a barrier layer in the second intaglio pattern and the at least a blind via, the barrier layer covering the first conductive layer;
forming a second conductive layer in the second intaglio pattern and the at least a blind via, the second conductive layer covering the barrier layer; and
removing parts of the second conductive layer, parts of the barrier layer, and parts of the first conductive layer until the second surface of the dielectric layer is exposed to form a patterned circuit structure, the patterned circuit structure being located in the first intaglio pattern, the second intaglio pattern, and the at least a blind via and being electrically connected to the at least a first circuit of the circuit substrate.

2. The manufacturing method as claimed in claim 1 , wherein a material of the dielectric layer comprises polymer.

3. The manufacturing method as claimed in claim 1 , wherein the laser beam is an infrared laser source or an ultraviolet laser source.

4. The manufacturing method as claimed in claim 1 , wherein a method of forming the first conductive layer comprises performing an electroless plating process.

5. The manufacturing method as claimed in claim 1 , wherein a method of forming the barrier layer comprises sputtering or chemical deposition.

6. The manufacturing method as claimed in claim 1 , wherein a material of the barrier layer comprises nickel, tin, chromium, aluminum, zinc, or gold.

7. The manufacturing method as claimed in claim 1 , wherein a method of forming the second conductive layer comprises performing an electroplating process.

8. The manufacturing method as claimed in claim 1 , wherein the patterned circuit structure comprises at least a second circuit and a plurality of third circuits, the at least a second circuit is located in the first intaglio pattern, the third circuits are located in the second intaglio pattern and the at least a blind via, a line width of the at least a second circuit is smaller than a line width of each of the third circuits, and at least one of the third circuits is electrically connected to the at least a first circuit of the circuit substrate.

9. The manufacturing method as claimed in claim 8 , wherein before the barrier layer is formed on the first conductive layer, the first intaglio pattern is filled with the first conductive layer to form the at least a second circuit of the patterned circuit structure.

10. The manufacturing method as claimed in claim 1 , wherein the step of removing the parts of the second conductive layer, the parts of the barrier layer, and the parts of the first conductive layer comprises:
performing a first etching process to remove one of the parts of the second conductive layer until the barrier layer is exposed;
performing a second etching process to remove the parts of the barrier layer until the first conductive layer is exposed; and
performing a third etching process to remove the parts of the first conductive layer and another one of the parts of the second conductive layer until the second surface of the dielectric layer is exposed.

11. The manufacturing method as claimed in claim 10 , further comprising performing a polishing process on the barrier layer before the second etching process is performed.

12. The manufacturing method as claimed in claim 1 , wherein the second intaglio pattern and the at least a blind via are connected.

Assignees

• Tseng Tzyy-Jang
• Chiang Shu-Sheng
• Chen Tsung-Yuan
• Unimicron Technology Corp

Inventors

• Tseng Tzyy-Jang
• Chiang Shu-Sheng
• Chen Tsung-Yuan

Classifications

• H05K3/107

  by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence) · CPC title

• H05K3/045

  by making a conductive layer having a relief pattern, followed by abrading of the raised portions · CPC title

• C23C18/1689

  After-treatment · CPC title

• H05K3/465 Primary

  by applying an insulating layer having channels for the next circuit layer · CPC title

• H05K1/0265

  characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections · CPC title