Diagnostic monitoring for analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-9509325-B1
Application number	US-201514706762-A
Country	US
Kind code	B1
Filing date	May 7, 2015
Priority date	May 7, 2015
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC), comprising:
a sampling circuit configured to convert an analog input to a digital output within a fault tolerance range; and
a channel selector having:
a reception channel configured to receive an analog signal, the reception channel having a channel impedance;
a diagnostic channel configured to receive a diagnostic signal for verifying the digital output of the sampling circuit;
a switch coupled with the reception channel and the diagnostic channel, and configured to select the reception channel or the diagnostic channel for providing the analog input to the sampling circuit; and
an impedance compensator coupled with the switch, the impedance compensator configured to offset the channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

2. The ADC of claim 1 , wherein the impedance compensator is coupled in series between the switch and the sampling circuit.

3. The ADC of claim 1 , wherein the impedance compensator is coupled in series between the diagnostic channel and the switch.

4. The ADC of claim 1 , wherein the impedance compensator has a compensatory impedance equal to or greater than a product of the channel impedance and the fault tolerance range.

5. The ADC of claim 1 , wherein:
the reception channel includes a first reception channel and a second reception channel, such that the first reception channel has a high channel impedance and the second reception channel has a low channel impedance; and
the impedance compensator is structured and routed to offset only the high channel impedance.

6. The ADC of claim 5 , wherein the switch includes:
a first switch coupled with the first reception channel, and configured to selectively link the first reception channel to a buffered channel;
a second switch coupled with the diagnostic channel and the impedance compensator, and configured to selectively link the diagnostic channel to the buffered channel;
a third switch coupled with the second reception channel, and configured to selectively link the second reception channel to the sampling circuit; and
a fourth switch coupled with the buffered channel, and configured to selectively link the buffered channel to the sampling circuit.

7. The ADC of claim 6 , wherein the channel selector includes a buffer having an input coupled with the first and second switches, and an output coupled with the fourth switch via the buffered channel, the buffer configured to:
amplify a high impedance signal defined by the first switch and the second switch; and
deliver the amplified signal to the buffered channel.

8. The ADC of claim 7 , further comprising:
a reference channel configured to provide a reference voltage for periodically resetting the input of the buffer; and
a reference switch configured to periodically couple the reference channel to the input of the buffer after a sampling cycle of the sampling circuit.

9. The ADC of claim 6 , wherein the channel selector includes a supplementary impedance compensator coupled with the fourth switch, the supplementary impedance compensator structured and routed to offset the low channel impedance of the second reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

10. The ADC of claim 8 , wherein the fourth switch includes:
a fifth switch configured to couple the supplementary impedance compensator in series between the buffered channel and the sampling circuit when the diagnostic channel is selected; and
a sixth switch coupled with the buffered channel, and configured to link the buffered channel with the sampling circuit when the first reception channel is selected.

11. A channel selector for use in an analog-to-digital converter having a sampling circuit configured to convert an analog input to a digital output within a fault tolerance range, the channel selector comprising:
a reception channel having a high channel impedance, and configured to receive an analog signal;
a first switch configured to selectively couple the reception channel with the sampling circuit;
a diagnostic channel configured to receive a diagnostic signal for verifying the digital output of the sampling circuit;
a second switch configured to selectively couple the diagnostic channel with the sampling circuit; and
an impedance compensator configured to offset the high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

12. The channel selector of claim 11 , wherein the impedance compensator is coupled in series with the diagnostic channel and the second switch, the impedance compensator having a compensatory impedance equal to or greater than a product of the high channel impedance and the fault tolerance range.

13. The channel selector of claim 11 , further comprising:
a second reception channel having a low channel impedance, and configured to receive a second analog signal;
a third switch configured to selectively couple the second reception channel with the sampling circuit when neither the first reception channel nor the diagnostic channel is selected;
a buffer having an input coupled with the first switch and the second switch, the buffer configured to amplifier a high impedance signal defined by the first and second switches, and configured to deliver the amplified signal to a buffered channel; and
a fourth switch coupled with the buffered channel, and configured to selectively couple the buffered channel with the sampling circuit when the second reception channel is not selected.

14. The channel selector of claim 13 , further comprising:
a reference channel configured to provide a reference voltage for periodically resetting the input of the buffer; and
a reference switch configured to periodically couple the reference channel to the input of the buffer after a sampling cycle of the sampling circuit.

15. The channel selector of claim 13 , further comprising:
a supplementary impedance compensator coupled with the fourth switch, the supplementary impedance compensator structured and routed to offset the low channel impedance of the second reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

16. A method for verifying a digital output of an analog-to-digital converter (ADC) having a channel selector configured to select a channel for providing an analog input, and a sampling circuit configured to convert the analog input to the digital output, the method comprising:
isolating the sampling circuit from the selected channel during a first time period;
resetting the sampling circuit during a second time period partially overlapping with the first time period;
coupling the sampling circuit with the channel selector during a third time period after the second time period and outside of the first time period, thereby allowing the sampling circuit to sample the selected channel; and
converting, using the sampling circuit, the sampled analog input to the digital output.

17. The method of claim 16 , further comprising:
resetting a high impedance output of the channel selector during a fourth time period after the third time period and partially overlapping with the first time period.

18. The method of claim 16 , wherein resetting the sampling circuit includes:
periodically charging an input capacitor of the sampling circuit to a refe

Assignees

• Texas Instruments Inc

Inventors

• Duryea Timothy Paul
• Garg Vaibhav

Classifications

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/12 Primary

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title