Multi-channel simultaneous sampling with a single ADC

Patent metadata

Field	Value
Publication number	US-9306790-B1
Application number	US-201414554699-A
Country	US
Kind code	B1
Filing date	Nov 26, 2014
Priority date	Jun 2, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A system includes an analog to digital converter (ADC) that samples an analog input signal as received by a first channel of a plurality of channels, samples the analog input signal as received by at least a second channel of the plurality of channels, and outputs a plurality of digital samples including a first set and a second set of digital samples of the analog input signal corresponding to the first channel and the second channel, respectively. A filter receives the first and second sets of digital samples, up-samples each of the first and second sets of digital samples, filters the up-sampled first set of digital samples and the up-sampled second set of digital samples, and outputs a first digital output signal and at least a second digital output signal based on the filtered first set of digital samples and the filtered second set of digital samples, respectively.

First claim

What is claimed is:

1. A system comprising:
a multiplexer that (i) receives an analog input signal on each of a first channel and a second channel of a plurality of channels, and (ii) selects between the first channel and the second channel to output the analog input signal;
an analog to digital converter (ADC) that samples the analog input signal as received from the multiplexer and outputs a plurality of digital samples including (i) a first set of digital samples of the analog input signal corresponding to the first channel and (ii) a second set of digital samples of the analog input signal corresponding to the second channel;
a demultiplexer that demultiplexes the plurality of digital samples output by the ADC into the first set of digital samples of the analog input signal corresponding to the first channel and the second set of digital samples of the analog input signal corresponding to the second channel; and
a filter that receives the first set of digital samples and the second set of digital samples from the demultiplexer, up-samples each of the first set of digital samples and the second set of digital samples, filters the up-sampled first set of digital samples and the up-sampled second set of digital samples, and outputs a first digital output signal and at least a second digital output signal based on the filtered first set of digital samples and the filtered second set of digital samples, respectively.

2. The system of claim 1 , wherein the ADC includes a successive approximation register (SAR) ADC.

3. The system of claim 1 , wherein the plurality of channels includes a plurality of input amplifiers that receive the analog input signal.

4. The system of claim 1 , wherein the plurality of channels include a plurality of low pass filters that receive the analog input signal.

5. The system of claim 1 , wherein the filter inserts a first delay into the first set of digital samples and a second delay into the second set of digital samples.

6. The system of claim 5 , wherein the filter adjusts at least one of the first delay and the second delay to align the first set of digital samples with the second set of digital samples.

7. The system of claim 1 , wherein the ADC samples the analog input signal as received by the first channel and the second channel at a sampling frequency that is less than a sampling frequency of the ADC.

8. The system of claim 7 , wherein the ADC samples the analog input signal as received by the first channel and the second channel at a sampling frequency of fs/n, where fs is the sampling frequency of the ADC and n is a number of the plurality of channels.

9. The system of claim 7 , wherein the filter up-samples each of the first set of digital samples and the second set of digital samples to the sampling frequency of the ADC.

10. The system of claim 7 , wherein, to up-sample each of the first set of digital samples and the second set of digital samples, the filter inserts at least one zero between samples of each of the first set of digital samples and the second set of digital samples.

11. The system of claim 1 , wherein the filter includes a first delay module and a second delay module that respectively delay the first set of digital samples and the second set of digital samples.

12. The system of claim 1 , wherein the filter includes a first low pass filter and a second low pass filter that respectively filter the up-sampled first set of digital samples and the up-sampled second set of digital samples.

13. The system of claim 1 , wherein the filter includes a first decimator and a second decimator that respectively decimate the filtered first set of digital samples and the filtered second set of digital samples.

14. A method comprising:
receiving an analog input signal on each of a first channel and a second channel of a plurality of channels;
selecting, using a multiplexer, between the first channel and the second channel to output the analog input signal;
using an analog to digital converter (ADC),
sampling the analog input signal as received from the multiplexer, and
outputting a plurality of digital samples including (i) a first set of digital samples of the analog input signal corresponding to the first channel and (ii) a second set of digital samples of the analog input signal corresponding to the second channel;

demultiplexing the plurality of digital samples output by the ADC into the first set of digital samples of the analog input signal corresponding to the first channel and the second set of digital samples of the analog input signal corresponding to the second channel;
up-sampling each of the first set of digital samples and the second set of digital samples;
filtering the up-sampled first set of digital samples and the up-sampled second set of digital samples; and
outputting a first digital output signal and at least a second digital output signal based on the filtered first set of digital samples and the filtered second set of digital samples, respectively.

15. The method of claim 14 , further comprising:
inserting a first delay into the first set of digital samples and a second delay into the second set of digital samples; and
selectively adjusting at least one of the first delay and the second delay to align the first set of digital samples with the second set of digital samples.

16. The method of claim 14 , wherein sampling the analog input signal as received by the first channel and the second channel includes sampling the analog input signal at the first channel and the second channel at a sampling frequency that is less than a sampling frequency of the ADC.

17. The method of claim 16 , wherein sampling the analog input signal as received by the first channel and the second channel includes sampling the analog input signal at the first channel and the second channel at a sampling frequency of fs/n, where fs is the sampling frequency of the ADC and n is a number of the plurality of channels.

Assignees

• Maxim Integrated Products

Inventors

• Strode Jonathan

Classifications

• H04L27/2663 Primary

  Coarse synchronisation, e.g. by correlation · CPC title

• H03M1/1225 Primary

  using time-division multiplexing · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title