Radiation-hardened-by-design (RHBD) multi-gate device

Patent metadata

Field	Value
Publication number	US-9508852-B2
Application number	US-201314781542-A
Country	US
Kind code	B2
Filing date	Sep 30, 2013
Priority date	Apr 3, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers. The interlayer has a doping type which is opposite to that of the substrate so that a shunt PN junction is formed between the interlayer and the substrate, and the shunt PN junction has an electrode not connected to the drain so that a part of the charges collected by the shunt PN junction are not output to the drain and are ultimately guided out of the multi-gate devices, thereby weakening the influence of the single-event effect. In comparison with a multi-gate device of prior art, the multi-gate device of the present invention may effectively suppress the sensitivity of the device to single event irradiation in the event that the layout areas of the two types of devices are almost same.

First claim

What is claimed is:

1. A radiation-hardened-by-design (RHBD) multi-gate device, comprising: a substrate ( 1 ); a source region ( 6 ) and a drain region ( 7 ), which are on the substrate and are positioned respectively at both ends thereof; a protruding fin structure ( 8 ) having two adjacent fins and a field dielectric layer ( 9 ) between the source region and the drain region on the substrate; a gate dielectric ( 10 ) on the protruding fin structure and the field dielectric layer; a gate electrode ( 11 ) covering the gate dielectric; two isolation layers ( 4 ) separated from each other, which are located in the drain region between the two adjacent fins, wherein an interlayer ( 5 ) is sandwiched between the two isolation layers.

2. The multi-gate device according to claim 1 , wherein the interlayer ( 5 ) has a doping type which is the same as that of the source region and the drain region and is opposite to that of the substrate ( 1 ).

3. The multi-gate device according to claim 2 , wherein a shunt PN junction is formed by the interlayer together with the substrate, and electrode of the shunt PN junction is led out by interconnection, and is not connected to a port of the drain.

4. The multi-gate device according to claim 3 , wherein n region of the shunt PN junction is connected to a high potential.

5. The multi-gate device according to claim 1 , wherein a material for isolation layer ( 4 ) is an insulation dielectric such as silicon oxide or silicon nitride.

6. The multi-gate device according to claim 1 , wherein the gate dielectric ( 10 ) has a cross-section of H type, Ω type, quadrilateral shape or cylindrical shape, etc.

Assignees

• Univ Beijing

Inventors

• Huang Ru
• Wu Weikang
• An Xia
• Tan Fei
• Huang Liangxi
• Feng Hui
• Zhang Xing

Classifications

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title