Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9508772-B2
Application number	US-201614995072-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Mar 25, 2010
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first material layer including a two-dimensional array area having a plurality of units arranged in a two-dimensional array and a first wiring layer;
a second material layer including a second wiring layer; and
a via passing through the first material layer and reaching a second interconnect provided in the second wiring layer,
wherein, the via has a first conductive portion and a second conductive portion, the first conductive portion is connected with a first interconnect provided in the first wiring layer and the second conductive portion is connected with the second interconnect,
wherein, a size of the second conductive portion is different from that of the first conductive portion.

2. The semiconductor device of claim 1 , further comprising:
a first insulating layer in the first material layer;
a second insulating layer in the second material layer, wherein, the second conductive portion extends into the second insulating layer in the second material layer, and the first conductive portion extends into the first insulating layer in the first material layer.

3. The semiconductor device of claim 1 , further comprising:
an on chip lens over a photodiode of the first material layer.

4. The semiconductor device of claim 3 , further comprising:
an on chip color filter between the photodiode and the on chip lens.

5. The semiconductor device of claim 1 ,
wherein the second conductive portion has a diameter that is different than a diameter of the first conductive portion along a common cross section parallel to an interface between the two material layers.

6. The semiconductor device of claim 1 ,
wherein the device is a backside illuminated device.

7. The semiconductor device of claim 1 ,
wherein the first material layer is a semiconductor layer.

8. The semiconductor device of claim 1 ,
wherein the second material layer is a semiconductor layer.

9. The semiconductor device of claim 1 ,
wherein the via is located within the two-dimensional array area.

10. The semiconductor device of claim 1 ,
wherein the second material layer includes a pad layer.

11. The semiconductor device of claim 10 ,
wherein the pad layer includes at least the second interconnect provided in the second wiring layer.

12. The semiconductor device of claim 1 ,
wherein a topmost layer of the second material layer is an aluminum interconnect layer.

13. The semiconductor device of claim 1 ,
wherein the second material layer includes signal input and output terminals.

14. The semiconductor device of claim 13 ,
wherein the signal input and output terminals are located along at least three sides of the second material layer.

15. The semiconductor device of claim 1 ,
wherein the two-dimensional array area includes a plurality of first and second vias.

16. The semiconductor device of claim 1 , further comprising a photodiode.

17. The semiconductor device of claim 1 ,
wherein each of the units in the two-dimensional array area is a photoelectric converter.

Assignees

• Sony Corp

Inventors

• Takahashi Hiroshi
• Sukegawa Shunichi
• Inoue Keishi

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title