Quantum well-modulated bipolar junction transistor

Patent metadata

Field	Value
Publication number	US-9508707-B2
Application number	US-201514630727-A
Country	US
Kind code	B2
Filing date	Feb 25, 2015
Priority date	Feb 27, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A semiconductor device includes a quantum well-modulated bipolar junction transistor (QW-modulated BJT) having a base with an area for a modulatable quantum well in the base. The QW-modulated BJT includes a quantum well (QW) control node which is capable of modulating a quantity and level of energy levels of the quantum well. A recombination site abuts the area for the quantum well with a contact area of at least 25 square nanometers. The semiconductor device may be operated by providing a reference node such as ground to the emitter and a power source to the collector. A bias voltage is provided to the gate to form the quantum well and a signal voltage is provided to the gate, so that the collector current includes a component which varies with the signal.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a semiconductor material;
a quantum well-modulated bipolar junction transistor (QW-modulated BJT), comprising:
a base of a first conductivity type disposed in the semiconductor material;
an emitter of a second, opposite, conductivity type abutting the base, disposed in the semiconductor material;
a collector of the second conductivity type abutting the base, disposed in the semiconductor material;
a quantum well control node disposed proximate to an area for a modulatable quantum well in the base, wherein the quantum well control node does not overlap the emitter or the collector; and
a recombination site abutting the area for the modulatable quantum well a contact area of at least 25 square nanometers.

2. The semiconductor device of claim 1 , wherein the semiconductor material is a silicon-containing Group IV semiconductor material.

3. The semiconductor device of claim 1 , wherein the recombination site is a dielectric layer disposed on a surface of the base.

4. The semiconductor device of claim 1 , wherein the quantum well control node is a gate disposed proximate to the area for the modulatable quantum well.

5. The semiconductor device of claim 4 , wherein the gate has a physical width less than 40 nanometers.

6. The semiconductor device of claim 1 , wherein:
the semiconductor material extends to a top surface of the substrate;
the base extends to the top surface;
the area for the modulatable quantum well in the base extends to the top surface and has an average doping density of 1×10 15 cm −3 to 3×10 18 cm −3 ;
the emitter is laterally adjacent to the base and extends to the top surface;
the collector is laterally adjacent to the base and extends to the top surface;
the recombination site is a gate dielectric layer disposed on the top surface, contacting the base; and
the quantum well control node is a gate disposed over the gate dielectric layer over the area for the modulatable quantum well.

7. The semiconductor device of claim 6 , wherein the base comprises:
a first barrier region at least 10 nanometers wide disposed between the area for the modulatable quantum well and the emitter, the first barrier region having the first conductivity type with an average doping density greater than 3×10 18 cm −3 , and extending to the top surface; and
a second barrier region at least 10 nanometers wide disposed between the area for the modulatable quantum well and the collector, the second barrier region having the first conductivity type with an average doping density greater than 3×10 18 cm −3 , and extending to the top surface.

8. The semiconductor device of claim 6 , comprising an n-channel metal oxide semiconductor (NMOS) transistor and a p-channel metal oxide semiconductor (PMOS) transistor.

9. The semiconductor device of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

10. The semiconductor device of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

11. A process of forming a semiconductor device, comprising the steps:
providing a substrate comprising a semiconductor material extending to a top surface of the substrate;
forming a base of a QW-modulated BJT in the semiconductor material extending to the top surface, the base having a first conductivity type, the base comprising an area for a modulatable quantum well;
forming barrier regions in the base on separate sides of the area for the modulatable quantum well, each barrier region being at least 10 nanometers wide and having average doping density greater than 3×10 18 cm −3 ;
forming an emitter of the QW-modulated BJT in the semiconductor material abutting the base, separated from the area for the modulatable quantum well by a first barrier region of the barrier regions, the emitter having a second, opposite, conductivity type;
forming a collector of the QW-modulated BJT in the semiconductor material abutting the base, separated from the area for the modulatable quantum well by a second barrier region of the barrier regions, the collector having the second conductivity type;
forming a gate dielectric layer on the top surface over the area for the modulatable quantum well, the gate dielectric layer providing a recombination site of the QW-modulated BJT with a contact area of at least 25 square nanometers to the area for the modulatable quantum well; and
forming a gate over the gate dielectric layer over the area for the modulatable quantum well, the gate having a physical width less than 40 nanometers, the gate providing a quantum well control node of the QW-modulated BJT.

12. The process of claim 11 , wherein the first conductivity type is p-type and the second conductivity type is n-type, and comprising the steps:
forming a first implant mask over the substrate which exposes areas for the barrier regions and areas for source/drain extensions of a PMOS transistor;
implanting p-type dopants into the substrate where exposed by the implant mask to form barrier implanted regions and source/drain extension implanted regions;
removing the implant mask; and
annealing the substrate to activate the p-type dopants in the barrier implanted regions to form the barrier regions and activate the p-type dopants in the source/drain extension implanted regions to form the source/drain extensions of the PMOS transistor.

13. The process of claim 11 , wherein the first conductivity type is p-type and the second conductivity type is n-type, and comprising the steps:
forming a first implant mask over the substrate which exposes an area for the emitter, an area for the collector, an area for a source of an NMOS transistor and an area for a drain of the NMOS transistor;
implanting n-type dopants into the substrate where exposed by the implant mask to form an emitter implanted region, a collector implanted region, a source implanted region and a drain implanted region;
removing the implant mask; and
annealing the substrate to activate the n-type dopants in the emitter implanted region to form the emitter, activate the n-type dopants in the collector implanted region to form the collector, activate the n-type dopants in the source implanted region to form the source of the NMOS transistor, and activate the n-type dopants in the drain implanted region to form the drain of the NMOS transistor.

14. The process of claim 11 , wherein the first conductivity type is n-type and the second conductivity type is p-type, and comprising the steps:
forming a first implant mask over the substrate which exposes areas for the barrier regions and areas for source/drain extensions of an NMOS transistor;
implanting n-type dopants into the substrate where exposed by the implant mask to form barrier implanted regions and source/drain extension implanted regions;
removing the implant mask; and
annealing the substrate to activate the n-type dopants in the barrier implanted regions to form the barrier regions and activate the n-type dopants in the source/drain extension implanted regions to form the source/drain extensions of the NMOS transistor.

15. The process of claim 11 , wherein the first conductivity type is n-type and the second conductivity type is p-type, and comprising the steps:
forming a first implant mask over the substrate which exposes an area for the emitter, an area for the collector, an area for a source of a PMOS transistor and an area for a drain of the PMOS transistor;
implanting p-type dopants into the substrate where exposed by the implant mask to form an em

Assignees

• Texas Instruments Inc

Inventors

• Edwards Henry Litzmann

Classifications

• H10D84/645

  Combinations of only lateral BJTs · CPC title

• H10D84/0119

  the components including complementary BJTs · CPC title

• H10D84/0109

  the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/184

  of lateral BJTs · CPC title