Electrical connector between die pad and z-interconnect for stacked die assemblies

Patent metadata

Field	Value
Publication number	US-9508689-B2
Application number	US-201514871185-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	May 20, 2008
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

First claim

We claim:

1. A method for forming a connector on a die pad at a wafer level of processing, comprising
forming a channel defining an interconnect die edge of a first die of the wafer and an adjacent edge of a second die of the wafer, wherein the interconnect die edge of the first die, the edge of the second die, and the channel therebetween have longest dimensions extending in a first direction, and a width of the channel extends in a second direction from the interconnect die edge to the adjacent edge of the second die;
forming an electrically insulative material overlying a front surface of the wafer, the interconnect die edge, and the edge of the second die, the insulative material spanning an entire width of the channel;
forming spots of a curable electrically conductive material over die pads and extending over an interconnect die edge above the channel;
curing the conductive material; and
in a wafer cutting procedure thereafter severing the spots.

2. The method of claim 1 , wherein the electrically insulative material is formed such that the die pads are exposed within openings in the electrically insulative material.

3. The method of claim 1 , wherein the spots are formed so as to span the entire width of the channel.

4. The method of claim 1 , wherein the spots are formed such that the spots do not span the entire width of the channel.

5. The method of claim 1 , such that the severed spots overhang the interconnect die edge.

6. The method of claim 1 , wherein the channel is a first channel, and the wafer cutting procedure forms a second channel which is narrower than the first channel.

7. The method of claim 1 , further comprising thinning the wafer subsequent to forming the channel.

8. The method of claim 7 , wherein the channel is formed to a depth greater than an eventual thickness of the die and less than a full wafer thickness prior to the thinning.

9. The method of claim 7 , further comprising applying a die attach film to the wafer after the thinning.

10. The method of claim 9 , further comprising cutting through the spots and die attach film.

11. A method for preparing a die for stacking and electrical connection, comprising:
performing a first wafer cutting procedure along first saw streets, thereby forming channels defining interconnect die edges of first die and adjacent edges of second die of a wafer, wherein each interconnect die edge, each adjacent edge of the second die, and each channel therebetween has a longest dimension extending in a first direction, and a width of each channel extends in a second direction from the interconnect die edge of a first die to the adjacent edge of a second die;
forming an electrically insulative material overlying a front surface of the wafer, the interconnect die edges, and the adjacent edges of the second die adjacent thereto, the insulative material spanning an entire width of each channel;
forming spots of an electrically conductive material over die pads and extending in a direction parallel to a front surface of the wafer beyond an interconnect die edge; and
in a second wafer cutting procedure thereafter severing the spots.

12. The method of claim 11 wherein the second wafer cutting procedure forms narrower channels than the first wafer cutting procedure.

13. The method of claim 11 , further comprising thinning the wafer subsequent to carrying out the first wafer cutting procedure.

14. The method of claim 11 wherein the first wafer cutting procedure is made to a depth greater than the eventual die thickness and less than the full wafer thickness, forming interconnect sidewalls.

15. The method of claim 11 , wherein the spots bridge the channel prior to being severed, and after being severed the spots include overhang portions extending beyond the interconnect die edge.

16. The method of claim 11 , wherein the severed spots include overhang portions extending beyond a surface of the electrically insulative material.

17. The method of claim 11 , wherein the spots are formed such that the spots do not span the entire width of the channel.

18. The method of claim 11 , such that the severed spots overhang the interconnect die edge.

Assignees

• Invensas Corp

Inventors

• Co Reynaldo
• Leal Jeffrey S
• Pangrle Suzette K
• Mcgrath Scott
• Melcher De Ann Eileen
• Barrie Keith L
• Villavicencio Grant
• Del Rosario Elmer M
• Bray John R

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/834

  Interconnections on sidewalls of chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title