Semiconductor package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9508565-B2
Application number	US-201514798833-A
Country	US
Kind code	B2
Filing date	Jul 14, 2015
Priority date	Jul 18, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

The semiconductor package according to an exemplary embodiment includes: a substrate having a plurality of circuit layers and connection pads which are provided between a plurality of insulating layers; a plated tail part of which one end is electrically connected to the connection pad; a dicing part provided in contact with the other end of the plated tail part; a molded part provided on the substrate; and molded part vias provided on the connection pads and penetrating through the molded part.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate comprising circuit layers and connection pads, which are provided between insulating layers;
a plated tail part comprising an end electrically connected to a connection pad of the connection pads;
a dicing part provided in contact with another end of the plated tail part;
a molded part provided on the substrate; and
molded part vias provided on the connection pads and penetrating through the molded part.

2. The semiconductor package of claim 1 , further comprising: vias configured to electrically connect the circuit layers to each other.

3. The semiconductor package of claim 1 , wherein the plated tail extends beneath an insulating layer, of the insulating layers, from the connection pad to reduce delamination of the connection pad.

4. The semiconductor package of claim 1 , wherein the plated tail forms an open line from the connection pad.

5. A method of manufacturing a semiconductor package, the method comprising:
preparing a substrate comprising openings for testing, circuit layers, and connection pads, which are provided between insulating layers;
forming a molded part on the substrate;
forming molded part via holes configured to expose upper portions of the connection pads and penetrate through the molded part; and
forming molded part vias by performing plating on the molded part via holes.

6. The method of claim 5 , wherein the substrate comprises: a plated tail part of which one end is electrically connected to a connection pad of the connection pads, and a dicing part formed to be in contact with another end of the plated tail part or to comprise a portion of the another end of the plated tail part.

7. The method of claim 5 , wherein the substrate comprises vias configured to electrically connect the circuit layers to each other.

8. The method of claim 6 , wherein the dicing part comprises the openings for testing.

9. The method of claim 5 , further comprising: after the preparing of the substrate, performing an open-short test.

10. The method of claim 5 , further comprising: before the forming of the molded part, forming solder balls in the openings for testing.

11. The method of claim 5 , further comprising: after the forming of the molded via holes, forming a seed layer by performing electroless plating on the molded part via holes and the openings for testing.

12. The method of claim 6 , further comprising: after the forming of the molded part vias, dicing the substrate in the dicing part to be separated into packages.

Assignees

• Samsung Electro Mech

Inventors

• Lim Jae Hyun
• Yoo Do Jae
• Jo Eun Jung

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/695 Primary

  Organic materials · CPC title