Computational wafer inspection

Patent metadata

Field	Value
Publication number	US-9507907-B2
Application number	US-201514730993-A
Country	US
Kind code	B2
Filing date	Jun 4, 2015
Priority date	Jun 10, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; and determining or predicting, using the actual value, an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect produced from the hot spot with the device manufacturing process.

First claim

The invention claimed is:

1. A defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising:
identifying a hot spot from the portion of the design layout;
determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot using the device manufacturing process;
determining an actual value of the processing parameter; and
determining or predicting, using the actual value and by a computer hardware system, an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect produced from the hot spot using the device manufacturing process.

2. The method of claim 1 , wherein the determining or predicting an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect further comprises using a characteristic of the hot spot, a characteristic of the design layout, or both, to determine or predict an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect.

3. The method of claim 1 , further comprising adjusting, or compensating for the processing parameter using the existence, the probability of existence, the characteristic, or the combination selected therefrom, of the defect.

4. The method of claim 3 , further comprising determining or predicting, using the adjustment of, or compensation for, the processing parameter, an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a residue defect produced from the hot spot using the device manufacturing process.

5. The method of claim 4 , further comprising indicating whether the hot spot is to be inspected at least partially based on the determined or predicted existence, probability of existence, the characteristic, or the combination selected therefrom, of the residue defect.

6. The method of claim 5 , further comprising inspecting the hot spot as produced on the substrate using the device manufacturing process.

7. The method of claim 1 , further comprising indicating whether the hot spot is to be inspected at least partially based on the determined or predicted existence, probability of existence, characteristic, or combination selected therefrom, of the defect produced from the hot spot using the device manufacturing process.

8. The method of claim 7 , further comprising inspecting the hot spot as produced on the substrate using the device manufacturing process.

9. The method of claim 1 , wherein the hot spot is identified using an empirical model or a computational model.

10. The method of claim 8 , wherein the hot spot is identified using a sensitivity of a pattern of the portion, with respect to the processing parameter.

11. The method of claim 1 , wherein the processing parameter is any one or more selected from: actual substrate stage position and/or tilt, actual reticle stage position and/or tilt, focus, dose, an illumination parameter, a projection optics parameter, data obtained from metrology, and/or data from an operator of a processing apparatus used in the device manufacturing process.

12. The method of claim 1 , wherein the determining or predicting an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect comprises simulating an image, or an expected patterning contour, of the hot spot under the processing parameter and determining an image parameter or contour parameter.

13. The method of claim 1 , wherein the identifying a hot spot includes identifying a location thereof.

14. The method of claim 1 , wherein the defect is undetectable before the substrate is irreversibly processed.

15. A method of manufacturing a device involving processing a pattern onto a substrate or onto a die of the substrate, the method comprising:
determining a processing parameter before processing the substrate or the die;
predicting or determining, by a computer hardware system, an existence of a defect, a probability of existence of a defect, a characteristic of a defect, or a combination selected therefrom, using the processing parameter before processing the substrate or the die, and using a characteristic of the substrate or the die, a characteristic of a geometry of a pattern to be processed onto the substrate or the die, or both; and
adjusting the processing parameter based on a prediction or a determination, obtained in the predicting or determining, so as to eliminate, reduce the probability of existence of, or reduce a severity of, the defect.

16. A defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising:
identifying a hot spot from the portion of the design layout;
determining or predicting, by a computer hardware system, an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect produced from the hot spot using the device manufacturing process; and
determining whether to inspect the hot spot at least partially based on a determination or a prediction of the existence, the probability of existence, the characteristic, or a combination selected therefrom, of the defect obtained in the determining or predicting.

17. A defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising:
identifying a hot spot from the portion of the design layout;
determining, by a computer hardware system, a sensitivity of the hot spot with respect to a processing parameter of the device manufacturing process for the hot spot;
generating a metrology mark having a substantially same value of the sensitivity; and
adding the mark into the design layout.

18. A method of defect prediction for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising:
determining an actual value of a processing parameter of the device manufacturing process; and
constructing, by a computer hardware system, an inspection map based at least partially on the actual value, wherein the inspection map comprises positions of potential defects on the substrate.

19. The method of claim 18 , further comprising inspecting the substrate at the positions of potential defects.

20. The method of claim 18 , wherein the constructing an inspection map further comprises simulating at least some of the potential defects using a process simulation model.

Assignees

• Asml Netherlands Bv

Inventors

• Fouquet Christophe David
• Kastrup Bernardo
• Den Boef Arie Jeffrey
• Mulkens Johannes Catharinus Hubertus
• Kavanagh James Benedict
• Koonmen James Patrick
• Callan Neal Patrick

Classifications

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G06N7/01

  Probabilistic graphical models, e.g. probabilistic networks · CPC title

• G03F7/7065

  Defects, e.g. optical inspection of patterned layer for defects · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G03F7/705 Primary

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title