Computer system with groups of processor boards

Patent metadata

Field	Value
Publication number	US-9507743-B2
Application number	US-201514748267-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Jan 31, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A computer system includes a plurality of printed circuit boards, each printed circuit board having one or more processor chips attached to the printed circuit board, wherein the number of printed circuit boards is an even number greater than or equal to 4, wherein the printed circuit boards are arranged in two groups, each group being arranged in a different stacking direction, and wherein the one or more processor chips which are attached to each one of the printed circuit boards of one of the groups are connected for communication to the processor chips of each printed circuit board of the other group.

First claim

The invention claimed is:

1. A method for connecting and communicating across a plurality of printed circuit boards of a computer system, each printed circuit board comprising two or more processor chips attached to the printed circuit board and a plurality of connectors, wherein a first subset of the two or more processor chips are connected to a first subset of the plurality of connectors and wherein a second subset of the two or more processor chips are connected to a second subset of the plurality of connectors, wherein the number of printed circuit boards is an even number greater than or equal to 4, the method comprising:
arranging the printed circuit boards in two groups, each group being arranged in a different stacking direction; and
connecting the two or more processor chips, which are attached to each one of the printed circuit boards of one of the groups, for communication to the processor chips of at least one printed circuit board of the other group.

2. The method according to claim 1 , wherein the communication across the processor chips is performed via at least one of:
a coherent shared memory access;
a non-coherent shared memory access;
providing access to a graphics, storage, communication or other adapter card attached via a PCI-interface;
message passing using a network protocol;
using communication between two or more processor chips on the same printed circuit board; and
at least one network router and a network interface controller connected to at least one processor chip on at least one printed circuit board.

3. The method according to claim 1 , wherein a printed circuit board is unconnected by previously idling its one or more processor chip via a hypervisor running on the computer system.

4. The method according to claim 1 , wherein the communication is tracked by a precise directory.

Assignees

• IBM

Inventors

• Steinmacher-Burow Burkhard

Classifications

• G06F13/1663

  Access to shared memory · CPC title

• H05K1/144

  Stacked arrangements of planar printed circuit boards · CPC title

• H05K2201/042

  Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• H05K2201/10159

  Memory · CPC title