Pulse-latch based bus design for increased bandwidth
US-2015363352-A1 · Dec 17, 2015 · US
US9507739B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9507739-B2 |
| Application number | US-201514922388-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 26, 2015 |
| Priority date | Jun 24, 2005 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
Opening claim text (preview).
What is claimed is: 1. A sub-system, comprising: an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the interface circuit configured to: interface the plurality of physical memory circuits and the system for emulating a virtual memory circuit having a refresh cycle time constraint that is different from a refresh cycle time constraint of the plurality of physical memory circuits; receive a refresh command from the system direct…
Physics · mapped topic
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