Home agent multi-level NVM memory architecture

Patent metadata

Field	Value
Publication number	US-9507534-B2
Application number	US-201113996668-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Systems and methods to implement a multi-level memory system having a volatile memory and a non-volatile memory are implemented. A home agent may control memory access to both a volatile main memory and a non-volatile second level memory. The second level memory may be inclusive of the main memory. In an embodiment, the home agent may be configured to manage the memory system in a low power state. In a low power state, the volatile memory may be shut down and the non-volatile memory utilized as the only local memory. In an embodiment, the home agent may be configured to manage error recovery for the main memory by recovering the data saved locally in the second level memory. In an embodiment, multiple cores may access the second level memory.

First claim

What is claimed is:

1. A method comprising:
receiving at a controller a transaction request from a processor comprising a command to access data stored in local memory;
determining if the data is in a main memory or a second level memory;
managing access to the local memory in response to the command, wherein data in the main memory is evicted to the second level memory in accordance with a cache coherence policy; and
managing the local memory in a low power mode by shutting down the main memory.

2. The method of claim 1 , further comprising:
maintaining inclusivity in the second level memory for data in the main memory.

3. The method of claim 1 , further comprising:
managing an error recovery policy for data in the main memory.

4. The method of claim 3 , further comprising:
recovering data causing an error in the main memory from the second level memory.

5. The method of claim 3 , further comprising:
periodically copying the state of the main memory to the second level memory.

6. The method of claim 1 , further comprising:
accessing the second level memory for each command received while in low power mode.

7. A system comprising:
a main memory unit comprising volatile memory;
a second memory unit comprising non-volatile memory;
a processor having an execution unit configured to execute commands to access data stored in either the main memory unit or the second memory unit; and
a controller coupled to the processor, the main memory unit and the second memory unit, the controller configured to receive transactions from the processor and to manage access to the main memory and the second to execute the transaction, the controller including logic to manage the system in a low power state by shutting down the main memory unit and to process transactions received from the processor with the second memory unit.

8. The system of claim 7 , wherein the second memory unit is inclusive of the main memory unit.

9. The system of claim 7 , the controller further comprising:
logic configured to manage error recovery for data in the main memory unit comprising recovering the data from the second memory unit.

10. The system of claim 9 , wherein the logic is configured to periodically copy the state of the main memory unit to the second memory unit.

11. The system of claim 7 , the controller further comprising:
logic configured to manage cache coherency for data in the main memory unit comprising copying data evicted from the main memory unit to the second memory unit.

12. The system of claim 7 , the controller further comprising:
logic configured to manage a cache coherency policy for the combined main memory unit and second memory unit.

13. The system of claim 7 , wherein the second memory unit comprises a PCM DIMM.

14. The system of claim 7 , wherein the main memory unit comprises a DDR DIMM.

15. The system of claim 7 , further comprising:
a second processor coupled to a second main memory unit and to the second memory unit.

16. A processor comprising:
a first memory unit comprising volatile memory;
a second memory unit comprising non-volatile memory;
a core having an execution unit configured to execute commands to access data stored in either the first memory unit or the second memory unit; and
a home agent coupled to the processor, the first memory unit and the second memory unit, the home agent configured to receive transactions from the core and to manage access to the first memory and the second memory to execute the transaction, the home agent comprising logic configured to manage the processor in a low power state comprising shutting down the first memory unit.

17. The processor of claim 16 , wherein the second memory unit is inclusive of the first memory unit.

18. The processor of claim 16 , the home agent further comprising:
logic configured to manage error recovery for data in the first memory unit comprising recovering the data from the second memory unit.

19. The processor of claim 16 , the home agent further comprising:
logic configured to manage cache coherency for data in the main memory unit comprising copying data evicted from the main memory unit to the second memory unit.

Assignees

• Ziakas Dimitrios
• Cai Zhong-Ning
• Intel Corp

Inventors

• Ziakas Dimitrios
• Cai Zhong-Ning

Classifications

• G06F12/08 Primary

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title