Integrated circuit to control a process and integrated circuit comprising control circuitry

Patent metadata

Field	Value
Publication number	US-9504040-B2
Application number	US-201514981252-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Aug 18, 2006
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A base station can prevent deterioration of data channel application control accuracy due to influence of transmission power control to a control channel. In the base station, each encoding section performs encoding processing to an SCCH (Shared Control Channel) of each mobile station, each modulating section performs modulation processing to the encoded SCCH, an arranging section arranges the SCCH to each mobile station to one of a plurality of subcarriers which configure an OFDM symbol, and transmission power control section controls transmission power of the SCCH based on reception quality information reported from each mobile station. The arranging section arranges a plurality of the SCCH to be under transmission power control to one of the subcarriers so that combinations at resource blocks are the same.

First claim

The invention claimed is:

1. An integrated circuit to control a process, the process comprising:
receiving data, which is transmitted from a base station and mapped on at least one of a plurality of blocks;
receiving a control channel among a plurality of control channels, which are respectively transmitted from the base station to different mobile terminals and mapped with a sequence to a frequency domain in units of the blocks, a plurality of subcarriers being divided into the plurality of blocks, and the plurality of control channels being arranged in the sequence cyclically shifted depending on a cell; and
transmitting reception quality information to the base station.

2. The integrated circuit according to claim 1 , comprising:
circuitry which, in operation, controls the process;
at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and
at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

3. The integrated circuit according to claim 2 , wherein transmission power of each of the plurality of control channels is controlled such that total transmission power of the plurality of control channels is fixed.

4. The integrated circuit according to claim 2 , wherein the plurality of control channels are mapped such that a sequence of the plurality of control channels is different between the plurality of blocks.

5. The integrated circuit according to claim 2 , wherein the plurality of control channels are mapped such that a sequence of the plurality of control channels is different between cells.

6. The integrated circuit according to claim 2 , wherein the plurality of control channels are mapped to a symbol other than a first symbol in a subframe.

7. The integrated circuit according to claim 2 , wherein the data is frequency-multiplexed with the plurality of control channels.

8. The integrated circuit according to claim 2 , wherein the plurality of control channels are mapped to a part of the plurality of blocks.

9. The integrated circuit according to claim 2 , wherein the plurality of control channels are mapped to a Localized Resource Block or a Distributed Resource Block.

10. The integrated circuit according to claim 2 , wherein the plurality of control channels are mapped such that each of the plurality of control channels is uniformly mapped to the plurality of blocks forming the frequency domain in units of the blocks.

11. The integrated circuit according to claim 2 , wherein the plurality of control channels are mapped such that a combination of the plurality of control channels which are mapped to two of the plurality of blocks is same between the two of the plurality of blocks.

12. The integrated circuit according to claim 2 , wherein each of the plurality of control channels carries control information including at least one of an ID of each of the different mobile terminals, a number of blocks that are allocated, information of modulation and coding scheme.

13. The integrated circuit according to claim 2 , wherein the at least one output and the at least one input, in operation, are coupled to an antenna.

14. An integrated circuit comprising:
circuitry, which, in operation:
controls reception of data, which is transmitted from a base station and mapped on at least one of a plurality of blocks, and reception of a control channel among a plurality of control channels, which are respectively transmitted from the base station to different mobile terminals and mapped with a sequence to a frequency domain in units of the blocks, a plurality of subcarriers being divided into the plurality of blocks, and the plurality of control channels being arranged in the sequence cyclically shifted depending on a cell; and
controls transmission of reception quality information to the base station.

15. The integrated circuit according to claim 14 , further comprising:
at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and
at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

16. The integrated circuit according to claim 15 , wherein transmission power of each of the plurality of control channels is controlled such that total transmission power of the plurality of control channels is fixed.

17. The integrated circuit according to claim 15 , wherein the plurality of control channels are mapped such that a sequence of the plurality of control channels is different between the plurality of blocks.

18. The integrated circuit according to claim 15 , wherein the plurality of control channels are mapped such that a sequence of the plurality of control channels is different between cells.

19. The integrated circuit according to claim 15 , wherein the plurality of control channels are mapped to a symbol other than a first symbol in a subframe.

20. The integrated circuit according to claim 15 , wherein the data are frequency-multiplexed with the plurality of control channels.

21. The integrated circuit according to claim 15 , wherein the plurality of control channels are mapped to a part of the plurality of blocks.

22. The integrated circuit according to claim 15 , wherein the plurality of control channels are mapped to a Localized Resource Block or a Distributed Resource Block.

23. The integrated circuit according to claim 15 , wherein the plurality of control channels are mapped such that each of the plurality of control channels is uniformly mapped to the plurality of blocks forming the frequency domain in units of the blocks.

24. The integrated circuit according to claim 15 , wherein the plurality of control channels are mapped such that a combination of the plurality of control channels which are mapped to two of the plurality of blocks is same between the two of the plurality of blocks.

25. The integrated circuit according to claim 15 , wherein each of the plurality of control channels carries control information including at least one of an ID of each of the different mobile terminals, a number of blocks that are allocated, information of modulation and coding scheme.

26. The integrated circuit according to claim 15 , wherein the at least one output and the at least one input, in operation, are coupled to an antenna.

Assignees

• Sun Patent Trust

Inventors

• Nishio Akihiko
• Fukuoka Masaru

Classifications

• H04W88/08

  Access point devices · CPC title

• H04L1/0009

  by adapting the channel coding (H04L1/1812 takes precedence) · CPC title

• H04W52/325

  Power control of control or pilot channels · CPC title

• H04L5/0005

  Time-frequency · CPC title

• H04W72/0453 Primary

  Resources in frequency domain, e.g. a carrier in FDMA · CPC title