Integrated circuit for controlling a process and integrated circuit comprising circuitry

Patent metadata

Field	Value
Publication number	US-9258802-B2
Application number	US-201514705677-A
Country	US
Kind code	B2
Filing date	May 6, 2015
Priority date	Aug 18, 2006
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A base station can prevent deterioration of data channel application control accuracy due to influence of transmission power control to a control channel. In the base station, each encoding section performs encoding processing to an SCCH (Shared Control Channel) of each mobile station, each modulating section performs modulation processing to the encoded SCCH, an arranging section arranges the SCCH to each mobile station to one of a plurality of subcarriers which configure an OFDM symbol, and transmission power control section controls transmission power of the SCCH based on reception quality information reported from each mobile station. The arranging section arranges a plurality of the SCCH to be under transmission power control to one of the subcarriers so that combinations at resource blocks are the same.

First claim

The invention claimed is:

1. An integrated circuit for controlling a process, the process comprising:
allocating at least one of a plurality of blocks to a communication party, a plurality of subcarriers being divided into the plurality of blocks;
mapping data to the at least one of the plurality of blocks; and
mapping a plurality of control channels, which are respectively addressed to different communication parties, with a sequence in which the plurality of control channels are arranged and which is cyclically shifted depending on a cell to a frequency domain in units of the blocks.

2. The integrated circuit according to claim 1 , comprising:
circuitry which, in operation, controls the process;
at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and
at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

3. The integrated circuit according to claim 2 , wherein the process further comprises controlling transmission power of each of the plurality of control channels such that total transmission power of the plurality of control channels is fixed.

4. The integrated circuit according to claim 2 , wherein the mapping includes mapping of the plurality of control channels such that a sequence of the plurality of control channels is different between the plurality of blocks.

5. The integrated circuit according to claim 2 , wherein the mapping includes mapping of the plurality of control channels such that a sequence of the plurality of control channels is different between cells.

6. The integrated circuit according to claim 2 , wherein the mapping includes mapping of the plurality of control channels to a symbol other than a first symbol in a subframe.

7. The integrated circuit according to claim 2 , wherein the mapping includes frequency-multiplexing of the data with the plurality of control channels.

8. The integrated circuit according to claim 2 , wherein the mapping includes mapping of the plurality of control channels to a part of the plurality of blocks.

9. The integrated circuit according to claim 2 , wherein the mapping includes mapping of the plurality of control channels to a Localized Resource Block or a Distributed Resource Block.

10. The integrated circuit according to claim 2 , wherein the mapping includes mapping of the plurality of control channels such that each of the plurality of control channels is uniformly mapped to the plurality of blocks forming the frequency domain in units of the blocks.

11. The integrated circuit according to claim 2 , wherein the mapping includes mapping of the plurality of control channels such that a combination of the plurality of control channels which are mapped to two of the plurality of blocks is same between the two of the plurality of blocks.

12. The integrated circuit according to claim 2 , wherein each of the plurality of control channels carries control information including at least one of an ID of the communication party, a number of blocks that are allocated, information of modulation and coding scheme.

13. The integrated circuit according to claim 2 , wherein the at least one output and the at least one input, in operation, are coupled to an antenna.

14. An integrated circuit comprising circuitry, which, in operation:
controls allocation of at least one of a plurality of blocks to a communication party, a plurality of subcarriers being divided into the plurality of blocks;
controls mapping of data to the at least one of the plurality of blocks; and
controls mapping of a plurality of control channels, which are respectively addressed to different communication parties, with a sequence in which the plurality of control channels are arranged and which is cyclically shifted depending on a cell to a frequency domain in units of the blocks.

15. The integrated circuit according to claim 14 , comprising:
at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and
at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

16. The integrated circuit according to claim 15 , wherein the circuitry, in operation, further controls transmission power of each of the plurality of control channels such that total transmission power of the plurality of control channels is fixed.

17. The integrated circuit according to claim 15 , wherein the mapping includes mapping of the plurality of control channels such that a sequence of the plurality of control channels is different between the plurality of blocks.

18. The integrated circuit according to claim 15 , wherein the mapping includes mapping of the plurality of control channels such that a sequence of the plurality of control channels is different between cells.

19. The integrated circuit according to claim 15 , wherein the mapping includes mapping of the plurality of control channels to a symbol other than a first symbol in a subframe.

20. The integrated circuit according to claim 15 , wherein the mapping includes frequency-multiplexing of the data with the plurality of control channels.

21. The integrated circuit according to claim 15 , wherein the mapping includes mapping of the plurality of control channels to a part of the plurality of blocks.

22. The integrated circuit according to claim 15 , wherein the mapping includes mapping of the plurality of control channels to a Localized Resource Block or a Distributed Resource Block.

23. The integrated circuit according to claim 15 , wherein the mapping includes mapping of the plurality of control channels such that each of the plurality of control channels is uniformly mapped to the plurality of blocks forming the frequency domain in units of the blocks.

24. The integrated circuit according to claim 15 , wherein the mapping includes mapping of the plurality of control channels such that a combination of the plurality of control channels which are mapped to two of the plurality of blocks is same between the two of the plurality of blocks.

25. The integrated circuit according to claim 15 , wherein each of the plurality of control channels carries control information including at least one of an ID of the communication party, a number of blocks that are allocated, information of modulation and coding scheme.

26. The integrated circuit according to claim 15 , wherein the at least one output and the at least one input, in operation, are coupled to an antenna.

Assignees

• Panasonic Ip Corp America

Inventors

• Nishio Akihiko
• Fukuoka Masaru

Classifications

• H04L5/0053

  Allocation of signalling, i.e. of overhead other than pilot signals · CPC title

• H04W52/325

  Power control of control or pilot channels · CPC title

• H04W24/10

  Scheduling measurement reports {; Arrangements for measurement reports} · CPC title

• H04W52/221

  using past power control commands · CPC title

• H04B7/12

  Frequency diversity · CPC title