Apparatus for offset trimming and associated methods

Patent metadata

Field	Value
Publication number	US-9503113-B1
Application number	US-201514732702-A
Country	US
Kind code	B1
Filing date	Jun 6, 2015
Priority date	Jun 6, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.

First claim

The invention claimed is:

1. An apparatus comprising:
a first circuit comprising a first transconductance stage to generate a first current, the first circuit having an output offset;
an offset trim circuit, comprising:
a second circuit to provide an output voltage selectable from a plurality of voltage values; and
a second transconductance stage to generate a second current in response to the output voltage of the second circuit;

wherein the output offset of the first circuit is trimmed by adding the second current to the first current.

2. The apparatus according to claim 1 , wherein the first circuit comprises a buffer.

3. The apparatus according to claim 1 , wherein the first circuit comprises an interpolator.

4. The apparatus according to claim 1 , wherein the first and second transconductance stages have corresponding transconductance values, and wherein the transconductance of the second transconductance stage is less than the transconductance of the first transconductance stage.

5. The apparatus according to claim 1 , wherein the second circuit in the offset trim circuit comprises at least one resistor coupled to a current source.

6. The apparatus according to claim 5 , wherein the at least one resistor comprises a plurality of taps to provide the plurality of voltage values, and wherein the second circuit in the offset trim circuit further comprises a plurality of switches coupled to corresponding taps in the at least one resistor.

7. The apparatus according to claim 6 , further comprising a controller to selectably control the set of switches to provide output voltage.

8. The apparatus according to claim 1 , wherein the first circuit is a buffer in a digital-to-analog converter (DAC) that converts a digital signal to an analog signal with monotonicity.

9. The apparatus according to claim 1 , wherein the first circuit is an interpolator in a DAC that converts a digital signal to an analog signal with monotonicity.

10. An apparatus comprising:
a digital-to-analog converter (DAC) to convert a digital input signal to an analog output signal, the DAC comprising:
a buffer to buffer a voltage and to provide a reference voltage;
a resistor DAC (RDAC) to provide first and second voltages in response to a first set of control signals and the reference voltage;
an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to a second set of control signals, the interpolator having a trimmable offset voltage; and
an offset trim circuit comprising a first transconductance stage to provide a first current to the interpolator to trim the offset voltage of the interpolator.

11. The apparatus according to claim 10 , wherein the buffer has a programmable offset voltage, and wherein the offset trim circuit further comprises a second transconductance stage to provide a second current to the buffer to trim the offset voltage of the buffer.

12. The apparatus according to claim 11 , wherein the offset trim circuit further comprises a first resistor with a first plurality of taps coupled to a first plurality of corresponding switches to provide a first selectable voltage to the first transconductance stage.

13. The apparatus according to claim 12 , wherein the offset trim circuit further comprises a second resistor with a second plurality of taps coupled to a second plurality of corresponding switches to provide a second selectable voltage to the second transconductance stage.

14. The apparatus according to claim 11 , wherein the interpolator comprises a transconductance stage having a transconductance higher than a transconductance of the first transconductance stage, and wherein the buffer comprises a transconductance stage having a transconductance higher than a transconductance of the second transconductance stage.

15. A method of trimming an offset, the method comprising:
generating a first current by using a first transconductance stage in a first circuit, the first circuit having an output offset;
providing a voltage selectable from a plurality of voltage values;
generating a second current in response to the voltage by using a second transconductance stage; and
trimming the output offset of the first circuit by adding the second current to the first current.

16. The method according to claim 15 , wherein the first circuit comprises a buffer.

17. The method according to claim 15 , wherein the first circuit comprises an interpolator.

18. The method according to claim 15 , wherein the first and second transconductance stages have corresponding transconductance values, and wherein the transconductance of the second transconductance stage is less than the transconductance of the first transconductance stage.

19. The method according to claim 15 , wherein generating the second current further comprises providing to the second transconductance stage a selectable voltage generated by a resistor coupled to a current source.

20. The method according to claim 19 , wherein providing to the second transconductance stage the selectable voltage further comprises selectably controlling a set of switches coupled to a corresponding set of taps in the resistor.

Assignees

• Silicon Lab Inc

Inventors

• Thomsen Axel
• Westwick Alan L
• Setiawan Ricky
• Ying Rex Wong Tak

Classifications

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03K5/003

  Changing the DC level (reinsertion of DC component of a television signal H04N5/16) · CPC title