Method of fabricating semiconductor light emitting device

Patent metadata

Field	Value
Publication number	US-9502605-B2
Application number	US-201514714223-A
Country	US
Kind code	B2
Filing date	May 15, 2015
Priority date	Oct 1, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method of fabricating a semiconductor light emitting device includes forming a first conductivity type semiconductor layer, forming an active layer by alternately forming a plurality of quantum well layers and a plurality of quantum barrier layers on the first conductivity type semiconductor layer, and forming a second conductivity type semiconductor layer on the active layer. The plurality of quantum barrier layers include at least one first quantum barrier layer adjacent to the first conductivity type semiconductor layer and at least one second quantum barrier layer adjacent to the second conductivity type semiconductor layer. The forming of the active layer includes allowing the at least one first quantum barrier layer to be grown at a first temperature and allowing the at least one second quantum barrier layer to be grown at a second temperature lower than the first temperature.

First claim

What is claimed is:

1. A method of fabricating a semiconductor light emitting device, comprising:
forming a first conductivity type nitride semiconductor layer;
forming an active layer on the first conductivity type nitride semiconductor layer; and
forming a second conductivity type nitride semiconductor layer on the active layer,
wherein the active layer has a structure in which a plurality of quantum barrier layers and a plurality of quantum well layers containing indium are alternately stacked,
the plurality of quantum barrier layers and the plurality of quantum well layers are divided into a plurality of groups according to a growth direction, and the plurality of groups respectively have at least one quantum barrier layer and at least one quantum well layer and include a first group adjacent to the first conductivity type nitride semiconductor layer and a second group adjacent to the second conductivity type nitride semiconductor layer, and
a quantum barrier layer of the first group is grown at a temperature higher than a growth temperature of a quantum barrier layer of the second group, a quantum well layer of the first group having an indium composition ratio lower than that of a quantum well layer of the second group.

2. The method of claim 1 , wherein the plurality of groups comprise a third group disposed between the first group and the second group, and a quantum barrier layer of the third group is grown at a temperature different from those of quantum barrier layers of the first and second groups.

3. The method of claim 2 , wherein the quantum barrier layer of the third group is grown at a temperature lower than a growth temperature of the quantum barrier layer of the first group and higher than a growth temperature of the quantum barrier layer of the second group.

4. The method of claim 3 , wherein a quantum well layer of the third group has an indium composition ratio higher than that of a quantum well layer of the first group and lower than that of a quantum well layer of the second group.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Sang Heon
• Lee Dong Yul
• Kim Seung Hyun
• Kim Jang Mi
• Yoon Suk Ho
• Lee Sang Jun

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title