Metallization of solar cells with differentiated P-type and N-type region architectures

Patent metadata

Field	Value
Publication number	US-9502601-B1
Application number	US-201615089382-A
Country	US
Kind code	B1
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region. Metallization methods, include etching techniques for forming a first and second conductive contact structure are also described.

First claim

What is claimed is:

1. A method of fabricating alternating N-type and P-type emitter regions of a solar cell, the method comprising:
forming a first silicon layer of a first conductivity type on a first thin dielectric layer formed on a back surface of a substrate;
forming an insulating layer on the first silicon layer;
patterning the insulating layer and the first silicon layer to form first silicon regions of the first conductivity type having an insulating cap thereon, wherein the patterning includes exposing an outer portion and a lateral portion of the first silicon regions;
forming a second thin dielectric layer on the back surface of the substrate;
forming a third thin dielectric layer on the exposed outer portion and lateral portion of the first silicon regions;
forming a second silicon layer of a second, different, conductivity type on the third thin dielectric layer, on the second thin dielectric layer, and on the insulating cap of the first silicon regions;
patterning the second silicon layer and insulating cap to form contact openings in regions of the second silicon layer and to expose portions of the first silicon regions;
forming a metal layer over the back surface of a substrate; and
patterning the metal layer and second silicon layer to form isolated second silicon regions of the second conductivity type and to form conductive contacts for the first silicon regions and the isolated second silicon regions, wherein the patterning includes etching the metal layer and the second silicon layer using same etchant.

2. The method of claim 1 , wherein the etchant is potassium hydroxide, tetramethylammonium hydroxide, ammonium hydroxide or sodium hydroxide.

3. The method of claim 1 , wherein etching the metal layer comprises etching a metal foil on the back surface of the substrate.

4. The method of claim 3 , wherein etching the metal foil on the back surface of the substrate comprises etching an aluminum foil on the back surface of the substrate.

5. The method of claim 1 , wherein etching the metal layer comprises etching an aluminum portion of metal seed layer.

6. The method of claim 1 , wherein the patterning includes etching the metal layer comprising aluminum and the second silicon layer having a conductivity type of N-type.

7. A solar cell fabricated according to the method of claim 1 .

8. A method of fabricating alternating N-type and P-type emitter regions of a solar cell, the method comprising:
forming a first silicon layer of a first conductivity type on a first thin dielectric layer formed on a back surface of a substrate;
forming an insulating layer on the first silicon layer;
patterning the insulating layer and the first silicon layer to form first silicon regions of the first conductivity type having an insulating cap thereon, wherein the patterning includes exposing an outer portion and a lateral portion of the first silicon regions;
forming a second thin dielectric layer on the back surface of the substrate;
forming a third thin dielectric layer on the exposed outer portion and lateral portion of the first silicon regions;
forming a second silicon layer of a second, different, conductivity type on the third thin dielectric layer, on the second thin dielectric layer, and on the insulating cap of the first silicon regions;
patterning the second silicon layer and insulating cap to form contact openings in regions of the second silicon layer and to expose portions of the first silicon regions;
forming a metal seed layer over the first silicon regions and on the second silicon layer;
forming a mask over the metal seed layer;
plating a metal layer on exposed portions of the metal seed layer;
removing the mask; and
etching the metal seed layer and second silicon layer to form isolated second silicon regions of the second conductivity type and to form conductive contacts for the first silicon regions and the isolated second silicon regions, wherein the etching comprises etching a portion of metal seed layer and the second silicon layer using same etchant.

9. The method of claim 8 , wherein the etchant is potassium hydroxide, tetramethylammonium hydroxide, ammonium hydroxide or sodium hydroxide.

10. The method of claim 8 , wherein the etchant has a weight percent of greater than 2% potassium hydroxide.

11. The method of claim 8 , wherein the etching comprises etching at a temperature in the range of 40-80 degrees Celsius.

12. The method of claim 8 , wherein the first and second silicon layers are formed as amorphous silicon layers, the method further comprising:
annealing the first and second silicon layers to form first and second polycrystalline silicon layers, respectively.

13. A solar cell fabricated according to the method of claim 8 .

14. A method of fabricating alternating N-type and P-type emitter regions of a solar cell, the method comprising:
forming a first silicon layer of a first conductivity type on a first thin dielectric layer formed on a back surface of a substrate;
forming an insulating layer on the first silicon layer;
patterning the insulating layer and the first silicon layer to form first silicon regions of the first conductivity type having an insulating cap thereon, wherein the patterning includes exposing an outer portion and a lateral portion of the first silicon regions;
forming a second thin dielectric layer on the back surface of the substrate;
forming a third thin dielectric layer on the exposed outer portion and lateral portion of the first silicon regions;
forming a second silicon layer of a second, different, conductivity type on the third thin dielectric layer, on the second thin dielectric layer, and on the insulating cap of the first silicon regions;
patterning the second silicon layer and insulating cap to form contact openings in regions of the second silicon layer and to expose portions of the first silicon regions;
forming a metal seed layer over the first silicon regions and on the second silicon layer;
forming a mask over the metal seed layer;
plating a metal layer on exposed portions of the metal seed layer;
removing the mask;
etching the metal seed layer using a first etchant; and
etching the second silicon layer using a second etchant including an oxidizer to form isolated second silicon regions of the second conductivity type and to form conductive contacts for the first silicon regions and the isolated second silicon regions, wherein the oxidizer inhibits etching of lateral portions of the metal seed layer.

15. The method of claim 14 , wherein the first or second etchant is potassium hydroxide, tetramethylammonium hydroxide, ammonium hydroxide or sodium hydroxide.

16. The method of claim 14 , wherein the first or second etchant has a weight percent of greater than 2% potassium hydroxide.

17. The method of claim 14 , wherein the etching with the first or second etchant comprises etching at a temperature in the range of 40-80 degrees Celsius.

18. The method of claim 14 , wherein the first and second etchant are the same etchant.

19. The method of claim 14 , wherein the oxidizer is hydrogen per oxide or ammonium peroxodisulphate.

20. A solar cell fabricated according to the method of claim 14 .

Assignees

• Smith David D
• Weidman Timothy
• Harrington Scott
• Balu Venkatasubramani
• Sunpower Corp

Inventors

• Smith David D
• Weidman Timothy
• Harrington Scott
• Balu Venkatasubramani

Classifications

• Y02E10/50

  Photovoltaic [PV] energy · CPC title

• H10F77/1228

  porous silicon · CPC title

• H10F77/707

  of the substrates or of layers on substrates, e.g. textured ITO layer on a glass substrate · CPC title

• H10F77/219 Primary

  Arrangements for electrodes of back-contact photovoltaic cells · CPC title

• H10F77/227

  for emitter wrap-through [EWT] photovoltaic cells, e.g. interdigitated emitter-base back-contacts · CPC title