Integrated fabrication of semiconductor devices

Patent metadata

Field	Value
Publication number	US-9502556-B2
Application number	US-201414321508-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Jul 1, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at opposing sides of the gate structure and an implant region for a resistor device is formed in the substrate. Pocket implant regions are formed in the source region and the drain region. A dielectric layer is formed to cover the gate structure and the substrate. A portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form lightly doped drain regions above the pocket implant regions. A resistor region of the resistor device is defined on the implant region. A portion of the dielectric layer is removed to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate comprising a gate structure;
performing a source/drain implant operation to form a source region and a drain region at opposing sides of the gate structure and an implant region for a resistor device in the substrate;
forming a plurality of pocket implant regions respectively in the source region and the drain region;
forming a dielectric layer to cover the gate structure and the substrate;
performing a heat treatment operation in which a portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form a plurality of lightly doped drain regions above the pocket implant regions;
defining a resistor region of the resistor device by locally masking the dielectric layer on the implant region; and
removing a portion of the dielectric layer to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region.

2. The method of claim 1 , wherein
the operation of providing the substrate comprises providing the substrate comprising a P type well;
the source/drain implant operation is performed to form the source region, the drain region and the implant region which are of N-plus type; and
the operation of forming the pocket implant regions comprises forming the pocket implant regions of P-plus type.

3. The method of claim 2 , wherein the operation of forming the lightly doped drain regions comprises forming the lightly doped drain regions of N-minus type.

4. The method of claim 1 , wherein
the operation of providing the substrate comprises providing the substrate comprising an N type well;
the source/drain implant operation is performed to form the source region, the drain region and the implant region which are of P-plus type; and
the operation of forming the pocket implant regions comprises forming the pocket implant regions of N-plus type.

5. The method of claim 4 , wherein the operation of forming the lightly doped drain regions comprises forming the lightly doped drain regions of P-minus type.

6. The method of claim 1 , wherein the operation of forming the dielectric layer comprises forming the dielectric layer comprising a first oxide layer, a nitride layer and a second oxide layer which are sequentially stacked.

7. The method of claim 1 , wherein the heat treatment operation is performed using a rapid thermal annealing process.

8. A semiconductor device, comprising:
a substrate;
an active device comprising:
a gate structure on the substrate;
a spacer on a sidewall of the gate structure;
a source region and a drain region at opposing sides of the gate structure in the substrate;
a plurality of lightly doped drain regions respectively in the source region and the drain region beneath the spacer; and
a plurality of pocket implant regions respectively in the source region and the drain region beneath the lightly doped drain regions; and

a resistor device comprising:
an implant region in the substrate;
a resistor protection dielectric layer on the implant region, wherein the resistor protection dielectric layer and the spacer are formed from the same material; and
a metal layer on the substrate and enclosing a sidewall of the resistor protection dielectric layer.

9. The semiconductor device of claim 8 , wherein each of the spacer and the resistor protection dielectric layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially stacked.

10. The semiconductor device of claim 8 , wherein the source region, the drain region and the implant region comprise the same dopant.

11. The semiconductor device of claim 8 , wherein
the substrate comprises a P type well;
the source region, the drain region and the implant region are of N-plus type;
the pocket implant regions are of P type or P-minus type; and
the lightly doped drain regions are of N-minus type.

12. The semiconductor device of claim 8 , wherein
the substrate comprises an N type well;
the source region, the drain region and the implant region are of P-plus type;
the pocket implant regions are of N type or N-minus type; and
the lightly doped drain regions are of P-minus type.

13. The semiconductor device of claim 8 , wherein the gate structure comprises a gate dielectric layer and a gate electrode which are sequentially stacked on the substrate.

14. A semiconductor device, comprising:
a substrate;
a core device, comprising:
a first gate structure on the substrate;
a first spacer on a sidewall of the first gate structure; and
a first source region and a first drain region at opposing sides of the first gate structure in the substrate;

an I/O device comprising:
a second gate structure on the substrate;
a second spacer on a sidewall of the second gate structure; and
a second source region and a second drain region at opposing sides of the second gate structure in the substrate, wherein the first source region, the first drain region, the second source region and the second drain region comprise the same dopant; and

a resistor device, comprising:
an implant region in the substrate;
a resistor protection dielectric layer on the implant region, wherein the resistor protection dielectric layer the first spacer and the second spacer are formed from the same material; and
a metal layer on the substrate and enclosing a sidewall of the resistor protection dielectric layer.

15. The semiconductor device of claim 14 , wherein each of the first spacer, the second spacer and the resistor protection dielectric layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially stacked.

16. The semiconductor device of claim 14 , wherein the first source region, the first drain region, the second source region, the second drain region and the implant region comprise the same dopant.

17. The semiconductor device of claim 14 , wherein
the core device further comprises:
a plurality of first lightly doped drain regions respectively in the first source region and the first drain region beneath the first spacer; and
a plurality of first pocket implant regions respectively in the first source region and the first drain region beneath the first lightly doped drain regions; and

the I/O device further comprises:
a plurality of second lightly doped drain regions respectively in the second source region and the second drain region beneath the second spacer; and
a plurality of second pocket implant regions respectively in the second source region and the second drain region beneath the second lightly doped drain regions.

18. The semiconductor device of claim 17 , wherein
the substrate comprises a P type well;
the first source region, the first drain region, the second source region, the second drain region and the implant region are of N-plus type;
the first pocket implant regions and the second pocket implant regions are of P type or P-minus type; and
the first lightly doped drain regions and the second lightly doped drain regions are of N-minus type.

19. The semiconductor device of claim 17 , wherein
the substrate comprises an N type well;
the first source region, the first drain region, the second source region, the second drain region and the implant region are of P-plus type;
the first pocket implant regions and the second pocket implant regions are of N type or N-minus type; and
the first lightly doped d

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Ming-Chi
• Yeh Yu-Lung
• Liang Chieh-Shuo
• Lin Shih-Chang
• Wu Meng-Yi
• Lin Hsing-Chih

Classifications

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title