Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control

Patent metadata

Field	Value
Publication number	US-9502521-B2
Application number	US-201113189225-A
Country	US
Kind code	B2
Filing date	Jul 22, 2011
Priority date	Nov 2, 2009
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.

First claim

The invention claimed is:

1. A method of forming a gate stack on a semiconductor substrate having a channel, the method comprising:
depositing a tunnel layer over the channel, wherein the tunnel layer comprises at least one silicon nitride compound having a chemical formula of Si x N y H z ;
depositing a charge trapping layer comprising a compound including silicon and nitrogen on top of the tunnel layer, the charge trapping layer comprising at least a first trapping sub-layer and a second trapping sub-layer, the first trapping sub-layer adjacent to the tunnel layer, the first trapping sub-layer having a first composition engineered to provide a low charge trap density to increase retention of information, the first composition comprising a nitrogen-rich silicon nitride compound and oxygen, the first composition having about the same as or more nitrogen on an atomic percentage basis than is present in stoichiometric silicon nitride, the silicon nitride compound present in the range of about 50% to less than 100% on an atomic percentage basis and oxygen present in the range of greater than 0% to about 50% on an atomic percentage basis, the second trapping sub-layer comprising a silicon-rich silicon nitride compound containing more silicon on an atomic percentage basis than is present in stoichiometric silicon nitride;
forming an interface region on the charge trapping layer, the interface region comprising a discrete layer with a compound including silicon, nitrogen and a charge blocking component selected from the group consisting of Al, Mg, Sr, Ba, Ti, Ta, Zr, Hf, Y, La and combinations thereof;
depositing a charge blocking layer on top of the interface region, the charge blocking layer containing an oxide of the charge blocking component included in the interface region; and
placing a control gate on top of the charge blocking layer.

2. The method of forming a gate stack of claim 1 , wherein depositing a tunnel layer over the channel comprises:
depositing a first tunnel sub-layer over the channel, the first tunnel sub-layer further comprising at least one component selected from the group consisting of SiO 2 and SiON;
depositing a second tunnel sub-layer on top of the first tunnel sub-layer, the second tunnel sub-layer comprising at least one component selected from the group consisting of Al 2 O 3 , MgO, SrO, BaO, TiO, Ta 2 O 5 , BaTiO 3 , BaZrO 3 , ZrO 2 , HfO 2 , Y 2 O 3 , ZrSiO 4 , HfSiO 4 , LaAlO 3 and Si x N y ; and
depositing a third tunnel sub-layer on top of the second tunnel sub-layer, the third tunnel sub-layer comprising at least one component selected from the group consisting of SiO 2 and SiON.

3. The method of forming a gate stack of claim 1 , wherein the first trapping sub-layer in deposited in a first chamber without air exposure; and
the second trapping sub-layer is deposited in the first chamber without air exposure.

4. The method of forming a gate stack of claim 3 , wherein forming the interface region comprises one or more of controlled oxidation of the second trapping sub-layer, oxidizing the second trapping sub-layer by exposing the second trapping sub-layer to air, and depositing a discrete interface region on top of the charge trapping layer in the first chamber without air exposure.

5. The method of claim 4 , wherein controlled oxidation of the second trapping sub-layer comprises one or more of oxidizing the second trapping sub-layer using wet oxidation, oxidizing the second trapping sub-layer using dry oxidation, oxidizing the second trapping sub-layer using radical oxidation, oxidizing the second trapping sub-layer using plasma oxidation, and oxidizing the second trapping sub-layer using oxygen implantation.

6. The method of forming a gate stack of claim 4 , wherein the first trapping sub-layer, the second trapping sub-layer and the interface region are deposited in separate chambers without air exposure between depositions.

7. The method of forming a gate stack of claim 1 , wherein the step of depositing a tunnel layer over the channel further comprises a tunnel layer having at least one compound selected from SiO 2 , Al 2 O 3 , MgO, SrO, BaO, TiO, Ta 2 O 5 , BaTiO 3 , BaZrO 3 , ZrO 2 , HfO 2 , Y 2 O 3 , ZrSiO 4 , HfSiO 4 and LaAlO 3 .

8. The method of forming a gate stack of claim 1 , wherein the step of depositing a tunnel layer over the channel further comprises a tunnel layer having SiON.

9. The method of forming a gate stack of claim 1 , wherein the step of depositing a tunnel layer over the channel comprises a tunnel layer having a thickness in the range of about 5 nm to 12 nm.

10. The method of forming a gate stack of claim 1 , wherein the step of forming the interface region between the charge trapping layer and the charge blocking layer comprises an interface region having a thickness in the range of about 1 nm to 5 nm.

11. The method of forming a gate stack of claim 1 , wherein the step of depositing a charge blocking layer comprises a charge blocking layer having a thickness in the range of about 10 nm to 15 nm.

Assignees

• Ganguly Udayan
• Olsen Christopher S
• Seutter Sean M
• Date Lucien
• Applied Materials Inc

Inventors

• Ganguly Udayan
• Olsen Christopher S
• Seutter Sean M
• Date Lucien

Classifications

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/685 Primary

  being perpendicular to the channel plane · CPC title

• H01L21/28282

  Electricity · mapped topic

• H01L29/513 Primary

  Electricity · mapped topic