Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor
US-9443926-B2 · Sep 13, 2016 · US
Method for preparing power diode
US9502497B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502497-B2 |
| Application number | US-201414902270-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 22, 2014 |
| Priority date | Oct 23, 2013 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method for preparing a power diode, including: providing a substrate ( 10 ), growing a N type layer ( 20 ) on the front surface of the substrate ( 10 ); forming a terminal protecting ring; forming an oxide layer ( 30 ), knot-pushing to the terminal protecting ring; forming a gate oxide layer ( 60 ), depositing a poly-silicon layer ( 70 ) on the gate oxide layer ( 60 ); depositing a SiO 2 layer ( 80 ) on the surface of the poly-silicon layer ( 70 ) and a oxide layer ( 50 ); forming a N type heavy doped region ( 92 ); forming a P+ region; removing a photoresist, implanting P type ions using the SiO 2 layer ( 80 ) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer ( 70 ), the gate oxide layer ( 60 ) being etched, and removing the SiO 2 layer ( 80 ); and processing a front surface metallization and a back surface metallization treatment. According to the method for preparing the power diode, by adjusting the isotropy etching level of the SiO 2 layer and the ion implanting dose and energy, the threshold voltage of a DMOS structure can be adjusted, and the adjustment of the forward voltage drop for the device can be achieved.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a power diode, comprising the following steps: providing a substrate, and growing an N-type layer on a front side of the substrate; forming a terminal guard ring on a front side of the N-type layer; forming an oxide layer on a surface of the front side of the N-type layer, and performing a driving-in to the terminal guard ring; performing photoetching by using an active region photomask, and etching the oxide layer on an activ…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9502497B2 cover?
- A method for preparing a power diode, including: providing a substrate ( 10 ), growing a N type layer ( 20 ) on the front surface of the substrate ( 10 ); forming a terminal protecting ring; forming an oxide layer ( 30 ), knot-pushing to the terminal protecting ring; forming a gate oxide layer ( 60 ), depositing a poly-silicon layer ( 70 ) on the gate oxide layer ( 60 ); depositing a SiO 2 lay…
- Who is the assignee on this patent?
- Csmc Technologies Fab1 Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D62/106. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).