Resin-encapsulated semiconductor device and its manufacturing method

US9502339B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9502339-B2
Application numberUS-201615015351-A
CountryUS
Kind codeB2
Filing dateFeb 4, 2016
Priority dateJan 30, 2007
Publication dateNov 22, 2016
Grant dateNov 22, 2016

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device ( 100 ) comprises a semiconductor chip ( 1 ) including a silicon substrate, a die pad ( 10 ) to which the semiconductor chip ( 1 ) is secured through a first solder layer ( 2 ), a resin-encapsulating layer ( 30 ) encapsulating the semiconductor chip ( 1 ), and lead terminals ( 21 ) electrically connected to the semiconductor chip ( 1 ) and including inner lead portion ( 21 b ) covered with the resin-encapsulating layer ( 30 ). The lead terminals ( 21 ) are made of copper or a copper alloy. The die pad ( 10 ) is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals ( 21 ).

First claim

Opening claim text (preview).

The invention claimed is: 1. A resin-sealed semiconductor device comprising: a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured; a sealing resin layer sealing the semiconductor chip; a plurality of lead terminals connected electrically with the semiconductor chip, one end portion of the plurality of lead terminals being covered by the sealing resin layer; and a plurality of suspension leads extending radially from corne…

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What does patent US9502339B2 cover?
A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device ( 100 ) comprises a semiconductor chip ( 1 ) including a silicon substrate, a die pad ( 10 ) to which the semiconductor chip ( 1 ) is secured through a first solder layer ( 2 ), a resin-encapsulating layer ( 30 ) encapsulating the semiconductor…
Who is the assignee on this patent?
Rohm Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/411. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).